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So I'm following this tutorial in which they explain some basic VHDL by using a four bit adder as an example:

-- Example of a four bit adder
library  ieee;
use  ieee.std_logic_1164.all;

-- definition of a full adder
entity FULLADDER is
     port (a, b, c: in std_logic;
           sum, carry: out std_logic);
     end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
     end fulladder_behav;
     -- 4-bit adder

library  ieee;
use  ieee.std_logic_1164.all;
entity FOURBITADD is
     port (a, b: in std_logic_vector(3 downto 0);
           Cin : in std_logic;
                sum: out std_logic_vector (3 downto 0);
                Cout, V: out std_logic);
     end FOURBITADD;
architecture fouradder_structure of FOURBITADD is
     signal c: std_logic_vector (4 downto 0);
component FULLADDER
           port(a, b, c: in std_logic;
sum, carry: out std_logic);
           end component;
begin
           FA0: FULLADDER
                port map (a(0), b(0), Cin, sum(0), c(1));
           FA1: FULLADDER
                port map (a(1), b(1), C(1), sum(1), c(2));
           FA2: FULLADDER
                port map (a(2), b(2), C(2), sum(2), c(3));
           FA3: FULLADDER
                port map (a(3), b(3), C(3), sum(3), c(4));
           V <= c(3) xor c(4);
           Cout <= c(4);
end fouradder_structure;

I am trying to understand why the component part in the fouradder_structure has to redefine the ports used in the FULLADDER entity; they both contain the following parts:

port(a, b, c: in std_logic;
sum, carry: out std_logic);

I then read somewhere that component defines the interface that the fouradder_structure is expecting. That would explain why entity and component both need to declare the used ports, but then how does the fouradder_structure know to use the FULLADDER entity that was defined previously? Is it a naming convention?

TL;DR, how is the architecture fouradder_structure aware it has to use the entity FULLADDER?

user1534664
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2 Answers2

7

If you don't specify which architecture an entity instantiation is going to use, it uses the most recently compiled architecture for that entity.

Personally I would use direct entity instantiation. To use this, delete the component declaration (component FULLADDER ...), and instantiate it thus:

FA0: entity work.FULLADDER(fulladder_behav)
port map ( ...

In this way you can easily see which architecture is being used, and you save yourself having to maintain a component declaration as well as the instantiation.

If you don't want to do this for some reason, look at using configurations.

scary_jeff
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1

You can control which entity (and which of its architectures) is bound to a specific component (provided they have compatible interfaces, i.e. port and generic lists) using a configuration statement. This can be either part of the architecture - an embedded configuration - or a separately compiled unit e.g. in a separate file.

If you don't bother with configurations, you 'll get the default configuration. Or you can bypass both components and configurations with direct entity instantiation - both of these approaches are described in Jeff's answer. (Direct entity instantiation is simplest and often seems to be the preferred approach nowadays).