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Update: the follow-up question shows my take on the resulting PCB layout.

I'm laying out my first board with a uC (I've got a reasonable amount of experience in using and programming embedded systems, but this is the first time I'm doing the PCB layout), an STM32F103, this will be a mixed-signal board using both the internal DACs of the STM and some external DACs via SPI, and I'm a bit confused about the grounding.

The answers to these questions:

clearly state that I should have a local ground plane for the uC, connected to the global ground at exactly one point, and a local power net, connected to the global power near that same point. So this is what I'm doing. My 4 layer stack is then:

  • local GND plane + signals, uC, it's 100nF decoupling caps, and the crystal
  • global GND, unbroken except for vias. In accordance to sources such as Henry Ott, the ground plane is unsplit, with the digital and analog sections physically separated.
  • power, a 3.3V plane under the IC, thick traces for the 3.3V external DACs, thicker traces for distributing the \$\pm15\$ volts in the analog section.
  • signal + 1uF decoupling caps

Further away on the board the analog components and signals are on the top and bottom layers.

So the questions:

  1. should I break the global ground under the uC, or is it good to have the full ground plane under the local one?
  2. Power plane: I'm intending to have a power plane only under the uC and use vias to bring the power to the decoupling caps and therefore the uC on the top layer, as I can't really use one much elsewhere. The external DAC's should be star distributed, so I have separate tracks for them, and the rest of the board is \$\pm15\$ volts. Does this sound ok?
  3. I'm using both the ADC and DAC of the uC, and generating a reference voltage in the analog section of the board, which I bring to the Vref+ pin of the uC with a track on the power plane. Where should I connect the Vref- pin: local ground, global ground, or make a separate track on the power plane connecting it to the global ground in the analog section, where the ground should be quiet? Maybe near to where the reference voltage is generated? Note that on the STM32 the Vref- is distinct from the analog ground VSSA pin (which I suppose goes to the local GND plane?).

Any other comments on the design here are of course welcome too!

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Timo
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  • A lot of searching questions resulting in a lot of good answers with good comments. However a lot of what is good practice can be learnt by studying what others have done. Take a lot of good quality (similar 4 layer) mixed signal PCBs and use a hor air tool to desolder large components. Investigate how the power vias are managed. You want to learn the best practice from professional designers as some of the stuff never gets into books, it is just in house rules of thumb, transmitted by oral and (over shoulder) proximity tradition. Do not pay as much attention to cheap consumer designs. – KalleMP Apr 28 '16 at 20:50

3 Answers3

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  1. No, you should not. And get rid of the so called "local ground". What do you think is happening with all the digital signals when you implement this local ground? You should find the answer in Henry Ott's article that you linked, Figure 1.

    Sure, you do have a connection between local ground and the ground plane, but all you do is increase the loop area, essentially turning your trances into small antennae.

  2. That sounds fine.

  3. The reference manual says that VREF- must be connected to VSSA which in turn must be connected to VSS. I suggest that you just connect the VREF- directly to ground and try to keep digital currents out of the way using clever placement.

As for the suggestions, if 1uF caps are the only components you plan to place on the bottom, I recommend that you place them on top. When you have components on both sides, the manufacturer either has to run the board through the oven twice, or solder the components by hand. Both of which will increase the manufacturing cost.

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Armandas
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  • You may want to include a link to the Ott article you're referencing. – akohlsmith Jan 09 '16 at 17:50
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    @akohlsmith I was referring to the same article as OP, but added a link now. – Armandas Jan 09 '16 at 17:53
  • There's quite a lot of components on the bottom in the analog section, so it's not just the big decoupling caps. – Timo Jan 09 '16 at 19:33
  • Sorry, I would have really wanted to accept half of your answer and half of Olin's if that were possible, but decided to go with Olin's since the local ground plane is what I ended up doing (as seen in the other question) – Timo Jan 12 '16 at 11:39
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You may find this answer useful.

There are a very few times I use truly separate planes (such applications still exist), but not for a circuit such as yours.

Careful placement of components and a bit of thought on the power / ground should help you achieve a good layout.

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Peter Smith
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You don't necessarily need a local ground plane for the micro. The local ground can be a star with the central point under the micro, which is where this star is connected back to the main ground, for example.

If you have at least 4 layers, then it can make sense to dedicate one of the layers in the immediate vicinity of the micro to a local ground. If this makes routing too hard or this is a two layer board, just use the star configuration. The main point is to keep the high frequency power current drawn by the micro off the main ground plane. If you don't do that, you have a center-fed patch antenna instead of a ground plane.

The loop from micro power pin, to bypass cap, to micro ground pin should not cross the main ground plane. This is where the high frequency power currents will run. Connect the ground pin to the main ground in one place, but do not connect the ground side of the bypass cap to the main ground separately. The ground side of the bypass cap should have its own connection back to the micro's ground pin.

Digital signals going between the micro and other parts of the board will still have small loop area because the micro will be connected to the main ground close to its ground pin.

Olin Lathrop
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    Olin, if you could post some references to back your "patch antenna" theory, that would be appreciated. – Armandas Jan 09 '16 at 18:14
  • In this specific case, how about the Vref- pin? To the local ground net/plane (I think I can do a plane, it'll take just a couple of more vias to keep the signal traces from breaking it entirely), or directly to the global one? – Timo Jan 09 '16 at 20:14
  • @Arm: It's just basic physics. – Olin Lathrop Jan 09 '16 at 21:59
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    @Timo: The Vref- pin draws very little current, and is used as the 0 reference for the A/D. This should be connected straight to the main ground plane with its own private via. – Olin Lathrop Jan 09 '16 at 22:01
  • @OlinLathrop Every complex open-source board I've seen (Novena, Intel Galileo, Paralella, iMX6 Rex, MicroZed and so on...) has a MCU/FPGA/DSP in the middle of the board and solid ground planes. Surely, if the problem you describe was significant, at least some of the designs would try to tackle it? – Armandas Jan 09 '16 at 22:26
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    @Arm: I'm not saying the ground plane shouldn't be solid. It's the way the processor's ground is connected to it that matters. Look closely, and you may see a local ground net with a single connection to the main ground. Also, a lot of times you can get away with less than best practises. Open source projects don't have to worry about the cost of field failures or that 1 in 10000 case where it doesn't work quite right, or even a lot of times about emission limits (not that it's legal, but much less likely the FCC is going to notice). – Olin Lathrop Jan 09 '16 at 23:16
  • @OlinLathrop Ok. Does this mean that the bypass caps for Vref+ also go directly to the main ground plane? Do the VSSA pin and ground of the VDDA bypass caps go the local or global plane? – Timo Jan 10 '16 at 12:09
  • I didn't find any mention in the datasheets as to how much current the VDDA pin will draw. – Timo Jan 10 '16 at 13:07
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    The issue with the Vref+ pin is that you want to keep noise off of it. You're not worried about it polluting the rest of the system. If you're using it, it's probably coming from a separate regulator anyway. You can connect the other side of its bypass cap to the main ground, or connect it to the analog ground pin if this chip has one, then connect that net to the main ground near the analog ground pin. – Olin Lathrop Jan 10 '16 at 14:08
  • @OlinLathrop how to apply local ground plane approach with BGA package? – Bip Jan 13 '16 at 15:14
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    @Bip: Again, the local ground isn't necessarily a plane. – Olin Lathrop Jan 13 '16 at 15:17
  • @OlinLathrop how about RF circuitry in QFN package i.e. bluetooth smart? Is it ok to connect central pad to local ground; capacitors on RF antenna trace direct to ground or local ground also? – Bip Mar 01 '16 at 12:41
  • @Bip complex BGA designs require a dense via field and freedom to run traces on the top layer to get to all the connections, a 4 layer board will be hard to route 'perfectly' but all one needs to do is segregate the low analogue signals from the rest with copper planes and tracks as much as possible. Having one of the layers a near complete ground plane is a reasonable design choice in many situations. Remember that modern designs would amount to black magic 30 years ago when computers had 'fast' networks with 10MBaud transitions. Things are kind of easier now. Add analogue filtering also. – KalleMP Apr 28 '16 at 20:56