I have an analog signal which ranges between 0V and 10V. I want to linearly scale it down to 0 to 2.5V for my ADC.
I'm concerned that using a resistive voltage divider will affect signal quality. Is this true? If it's not true, what value resistor should I use for voltage divider?
Yes, a voltage divider is fine in theory. How much it effects signal quality is in large part dependent on what you consider a quality signal. Is this HiFi audio, a digital data stream, voice audio, RF, something else?
There are several issues with resistive voltage dividers you should be aware of:
In this case R1 = 3*R2. The impedance looking into the divider from the source will be R1+R2. You have to make sure this is high enough to not load the source signal to change its characteristics to the point you care. For example, if R1=30kΩ and R2=10kΩ, then the divider will load the source with 40kΩ.
One way to deal with this is to add deliberate capacitance as small as possible but several times the expected stray capacitance so that the total capacitance becomes predictable. The capacitance accross each resistor must be inversely proportional to that resistance. For example, here is a nicely ballanced voltage divider:
At low frequencies, the resistors dominate and divide the signal by 4. At high frequencies, the capacitors dominate and divide the signal by 4. The crossover where the resistive and capacitive actions are about equal is 53 kHz in this example.
By the way, this is how dividing scope probes work. A "10x" probe divides the signal by 10. Since it needs to do that accross the scope's whole frequency range, a little capacitance is added to each resistor. The stray capacitance can never be exactly known and there will be some part tolerance anyway, so one of the capacitors is made variable. This is what the "probe compensation" adjustment is. This adjustment turns a small trim cap of a few pF. With a square wave in, you can see easily see the point where the capacitive and resistive dividers match.
One drawback of this capacitive and resistive approach is that the impedance of the divider goes down at high frequencies. While this approach is useful for properly dividing higher frequencies, it also loads them much more than just two resistors would. There is no free lunch.
Hopefully you can see some of the issues and tradeoffs now. If the impedances don't work out, then you need to consider some kind of active buffering like Steven already described. That has it's own set of issues, like offset voltage, frequency response, and gain error if gain is not just 1, but those are for another thread.
Basically, what you're trying to do is called "signal conditioning". It generally goes like this:
First, buffer the signal. Unless your 0-10 V source has a low output impedance already, buffer it with a noninverting op amp (see stevenvh's answer). Make sure the op amp has enough bandwidth. Usually this is described as a "gain-bandwidth product" since the spec is the gain of the circuit times the bandwidth. This isn't always the case; some amplifiers are current-mode and have a graph showing gain vs. bandwidth. Your case is simple: the gain is 1, so if a gain-bandwidth product is specified, it's also the bandwidth at a gain of 1.
Next, divide the output down by 4 using a resistor divider. Since you're using an ADC, you need to be careful about signal aliasing (noise also aliases, so even if your signal is well below the ADC Nyquist frequency, you should still have an anti-aliasing filter). The easiest anti-aliasing filter is to just put a capacitor from your divider's output to ground and treat it as an RC filter, where the R is equal to the divider's two resistor values in parallel. The corner should be past the highest frequency you want to pass to the ADC, and the filter should attenuate by 6 dB per bit by the time it reaches the aliasing frequency (which is the sample rate minus the filter corner frequency).
Here's where your ADC type matters. In a normal successive-approximation ADC (SAR), the sample rate is much, much lower than in a sigma-delta ADC, so the 20 dB/decade you get with an RC filter might not be enough. If that's the case, then you need to get a more complex multiple-pole filter in there. That's a huge discussion in itself, so I'll skip over it for now; look up complex-pole filters and download a copy of TI's FilterPro if you're interested.
Once your signal is filtered, you may need to buffer it again if the filter's output impedance isn't much lower than the ADC input impedance. Finally, if your ADC input has a different DC offset from your input, you'll need a DC-blocking (i.e. series) capacitor. This should be chosen as if the ADC's input impedance is the resistor in a RC high-pass filter; make sure the filter corner is below your minimum input frequency.
You want to divide the signal by a factor 4, which is easy with a resistor divider. The resistor at the input should be 3 times that to ground. Exact value depends on the ADC's input impedance. This is usually not very high, so the input impedance may distort the divider. Say you pick 10k\$\Omega\$ and 3.3k\$\Omega\$ for the resistors. This will give you 2.5V out for 10V input. Nice. But suppose the ADC's input impedance is also 3.3k\$\Omega\$. This is parallel to the 3.3k\$\Omega\$ resistor of your divider, resulting in 1.65k\$\Omega\$, so that you divide by 7 instead of 4.
So you'll have to increase the 3.3k\$\Omega\$ so that the combined resistance with the ADC's input impedance will be 3.3k\$\Omega\$.
Alternatively, you can buffer the divider with a voltage follower, like Matt suggests:
