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I am developing a pipeline block for inclusion in an ASIC. I want to decide between designing the block as a Mealy machine or as a Moore machine.

Does this choice have implications for timing closure?

No answer here: How to choose between Mealy and Moore state machine

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Brent Bradburn
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    My preference : Neither. The (VHDL) single-process form of state machine leads to all outputs being registered, which gives the cleanest timings, thus the best option for timing closure. –  Jan 07 '16 at 20:13
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    @BrianDrummond: "all outputs being registers" -- wouldn't that make it a **Moore machine** -- _whose output values are determined solely by its current state_? – Brent Bradburn Jan 07 '16 at 22:01
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    You could call it a subset of a Moore machine. A general Moore machine can derive outputs from the current state using combinational logic - adding gate delays to the timing model (and the possibility of glitches on an output when 2 state bits change). This is often acceptable of course, but not "best" where timing closure is difficult. –  Jan 07 '16 at 22:23
  • @BrianDrummond: I found [this slide](https://courses.cs.washington.edu/courses/cse567/98au/ppt/05b-sequential/sld004.htm) on multiple sites in which what you describe is referred to as _"Registered Mealy Machine (Really Moore)"_. – Brent Bradburn Jan 08 '16 at 05:38
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    hehe ... I call it neither, that slide calls it both! Take your pick... Seriously though, any time you see a fierce debate over the merits of Mealy versus Moore, you know you're in academic fairyland, not practical engineering. Just write it, simulate it, synthesise it, done. Single clocked process is simpler, cleaner, less prone to accidental bugs, and registers all outputs. (I've seen some books that regard the latter as a disadvantage - without justification :-) –  Jan 08 '16 at 11:34
  • Related: http://electronics.stackexchange.com/q/186472/16776 – Brent Bradburn Jan 08 '16 at 20:04
  • Useful answer to a different question: http://electronics.stackexchange.com/a/96536/16776 – Brent Bradburn Jan 08 '16 at 20:11

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