What was the motivation for making behavioral descriptions such a big part of Verilog?

Question

I don't use Verilog for anything serious, but I use it in my classes, and I'm starting to think I must be missing something about the appeal of behavioral hardware description.

When I write Verilog I feel like behavioral description is solving the easy problem, namely making a structural description of the hardware; and I'm not really sure if it makes it much easier. But I do find myself spending a lot of time checking and rechecking my ifs and cases to make sure they're really combinatorial when I want them to be.

Maybe I'm just not designing the right kind of hardware to make always blocks convenient?

Answer 1

You have to remember that although hardware synthesis is important, the true reason for the existence of Verilog (and VHDL for that matter) is simulation.

These languages are designed to allow users to model and understand their hardware, often before it's even created. They allow entire systems to be analyzed and their designs tweaked to perfection. Then, the hardware model can be transformed into something synthesizeable. With the design model, the synthesis model, and the appropriate tests, the user is able to be sure that proposed hardware definition fully implements their design.

All the crazy (and not so crazy) features of Verilog that you aren't yet using, are there to make writing hardware models (relatively) easy.

Answer 2

Problems like synthesis of unintended latches plagued Verilog. Fortunately, SystemVerilog, the successor of Verilog, rectifies these problems:

• In SystemVerilog, the successor of Verilog, always_ff is used for sequential logic synthesis, always_latch for latched logic synthesis and always_comb for combinational logic synthesis instead of the general always blocks.

• These blocks automatically check and report if the wrong logic is in the block during compilation, i.e. if latched logic is in the always_comb block instead of combinational logic due to missing if or case conditions.

• SystemVerilog also has different kinds of if and case statements like priority and unique which aid in synthesisizing combinational logic like priority and non-priority decoders.