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I'm trying to get rid of a clkgate timing violation. I have two of them and those are really big violations as you can see in this report:

+--------------------+---------+---------+---------+---------+---------+---------+
|     Hold mode      |   all   | reg2reg | in2reg  | reg2out | in2out  | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|           WNS (ns):|-157.134 |  0.001  |  0.751  |  0.013  |   N/A   |-157.134 |
|           TNS (ns):|-158.993 |  0.000  |  0.000  |  0.000  |   N/A   |-158.993 |
|    Violating Paths:|    2    |    0    |    0    |    0    |   N/A   |    2    |
|          All Paths:|  2951   |  2792   |   98    |   18    |   N/A   |   44    |
+--------------------+---------+---------+---------+---------+---------+---------+

Those violations are due to clock gating if I well understood the documentation but there is no more information about the resolution of this type of violation. The violated paths are related to a clock path between a JTAG and a memory.

I tried to use the -clkGateAware option in order to place the cells differently but it didn't help. I already tried to compile multiple time (10x in a row in the hold optimization bloc) but it didn't solve the issue...

What can be the cause of a violation as big as this one ? Is there a simple option that I can use to solve this issue ? Can someone suggest something clever to get rid of this type of clkgate ?

EDIT: To be clearer: My project is composed of an ARM M0, two SRAM, an HW Accelerator and a SPI. There is also a JTAG slave in order to program the memory with the code for the M0.

All those peripherals are connected to the AHB bus and are working fine. The synthesis is OK without any violation path. However, when I try to place and route the design, the clock gating occurs in order to reduce the power consumption. This also adds violating paths (two). So my question is more related to Encounter and the optimization commands: Is there something I can do in order to avoid this violated path ?

Winston Smith
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Gp2mv3
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  • Can you please give more of the context on what you're trying to do? –  Dec 28 '15 at 10:35
  • I edited my post with more details – Gp2mv3 Dec 28 '15 at 13:11
  • Does your clock tree extend beyond the clock gates? This is generally a common problem, where the CTS does not trace through the clock tree and branches get unbalanced. I'd check that. – deadude Dec 28 '15 at 13:15
  • How can I check this ? – Gp2mv3 Dec 28 '15 at 13:21
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    Fire up the gui mode and halt the script just after clock tree synthesis, you can use the menu option to display your clock tree. See if it extends to the all intended flipflops. – deadude Dec 29 '15 at 06:51
  • You have two violations in the clkgate group. One is 157.134, so the other must be 1.859 (to sum to 158.993 TNS). You should do a detailed report (including clock paths) of the timing path with the 157.134 violation. I would assume that there's something fishy with the clock definitions between the logic driving the clock enable logic and the clock on the clock gate itself. I.e., they are different or highly skewed clocks. – Winston Smith Jan 05 '16 at 00:57
  • I found the issue, I omitted a clock definition in my sdc file. Sorry for that... – Gp2mv3 Jan 05 '16 at 21:23

1 Answers1

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Simple solution is to slow the clock down. A more complex solution is to use gate types which do not violate the setup time, swap them out if possible. Physically moving them closer in route and place might also be an option.

Robert Hana
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