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I was told in the university that bus contention can cause hardware damage. I am referring to a situation where two pieces of hardware force/drive different logic levels on the same signal.

Taking example of an FPGA that is connected to a PS2 device or any other example where using bidirectional signals is required, what will happen if both the devices on this bidirectional signal drive different logic levels onto it?

quantum231
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2 Answers2

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Just like you were told. If one device tries to pull high whilst the other tries to pull low the current will flow at will up to a level determined by the silicon resistance of the two output structures on the devices. Some devices may have current limit designed into them but even then the current is very likely to be way higher than the specified safe limit for the parts.

High current flow like this can quickly build up heat to a level that destroys the IC chip in the area around the pin connection. In some cases the failure could destroy the whole chip. In others there may be parts of the IC that remain functional with loss of some pins functionality.

If you are trouble shooting a board that was just built and has a contention issue due to a wrong connection or solder short it is often possible to fix the bad connection and have the board function normally. However it is always possible that the affected devices will have been stressed some and they could fail at some later time. Metal migration on chip could happen to create a short or stress could have damaged an oxide so that it fails when there is a transient at power on or power off time.

Michael Karas
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  • I see, This explains why my teacher type me to avoid bidirectional ports in VHDL – quantum231 Dec 23 '15 at 18:37
  • I understand that one of the buyers will sink current while the other will source it. Shouldn't both only be capable of sourcing current and not sinking any? Hmmm – quantum231 Dec 23 '15 at 18:38
  • @quantum231 - The point of the contention discussion is that the two drivers in question will be set to have one sourcing and one sinking (ie one high and the other as low output). Of course the logic could set both drivers high or both low but then of course there would not be any contention. If your thought was that the drivers should automatically switch to the same state to avoid contention that would lead to a system that would not properly respond to its inputs. Afterall when the inputs to the driver says "go high" we expect the driver to follow those orders and (continued) – Michael Karas Dec 23 '15 at 20:34
  • (continued from above) set its output high. Likewise when the inputs to the other driver say "go low" we expect the driver outputs to follow and go low. – Michael Karas Dec 23 '15 at 20:44
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Yes, an FPGA can be damaged if there is another device driving a different voltage onto a pin that it is using as an output.

Will it happen the very first time you do that? Probably not.

Should you ever design something where this happens as part of the designed behavior? I'd say no.

The Photon
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  • I just realized there is a catch. I am dealing with PS2 protocol. This means that the two devices shall either pull down or be high impedance and the logic high results only from the pull high resistor. Therefore, nothing should get damaged as no bus contention can occur. – quantum231 Dec 23 '15 at 18:53
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    @quantum231, yes, open-drain logic is often used on shared buses for this reason. The problem is that open-drain requires a possibly bad trade-off between power consumption and speed. – The Photon Dec 23 '15 at 18:57
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    @ThePhoton Which is a complete non-issue for PS/2, which runs at 10-16 kHz. –  Dec 23 '15 at 19:08
  • @duskwuff, I have no idea what PS/2 protocol is. That's why I said it was a "possibly" bad trade-off, not that it would be a bad trade-off for OP's situation. – The Photon Dec 23 '15 at 20:04
  • Ok this if clear. Since I don't want to damage my board I will ask just this one question. I can see from the cyclone iv device handbook that a pin can inherently behave as a bidirectional pin. As long as I write vhdl code to only read an inout buffer and then set its value to 'z' i.e tristate, my fpga will not get damaged as it will not drive any logic value on the pin. – quantum231 Dec 23 '15 at 20:12
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    Yes, for pseudo-open-drain bidirectional you need to always set the value to either 0 or Z. – The Photon Dec 23 '15 at 21:27