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As I know, the setup time is at least required time for data to become stable at the input of a FF before the sensitive clock edge. Hold time is the required time for data to remain stable after the clock edge.

Usually I use a clock from a 24MHz OSC, when I use a test board. But when I synthesize with the RTL to make a chip, I used to 88MHz to 120MHz. I think this is meaning that this board can work at almost 120MMz.

Then what if I want to make a chip with RTL that works at almost 800MHz frequency, then is this meaning that the Flip-Flop is working in 800MHz?

If yes, which fab companies support that frequency? Is this possible way? Is this needed some unique process in a fab?

Tom Carpenter
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bural
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    The answer is, "it depends". There is a *lot* of information missing that is needed to answer that, but think about this, what frequency does the CPU in your computer run at? I'll bet you its over 2GHz nowadays. – Tom Carpenter Dec 15 '15 at 02:27

2 Answers2

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Here is a D flip-flop spec'ed to operate at 40 Gbps. Setup and hold times are advertised as 4 ps. It consumes only about 750 mW.

These are manufactured with a SiGe process, although I don't know which one.

There are several foundries offering SiGe process, including GlobalFoundries, TSMC, and TowerJazz.

The Photon
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  • Note that at these speeds, an extra 1 mm of wire length will degrade setup or hold times by an additional 4 ps. – jp314 Dec 15 '15 at 03:19
  • @jp314, at these speeds you're going to play a lot of games to get your clock and data aligned. – The Photon Dec 15 '15 at 04:03
  • *only* 750 mW? I laughed at that number, but then wondered if you were being sarcastic or considered that low for SiGe? I don't know much about that process myself... – Jonathan Drolet Dec 31 '15 at 04:38
  • @JonathanDrolet, yes, sarcasm. 750 mW is a heck of a lot for a single D flip-flop. But when you want 40 Gbps, you do what you have to do. – The Photon Dec 31 '15 at 06:09
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(the below is my understanding of the situation, but I only do FPGA design not ASIC so some bits may be a bit vauge)

Yes flip flops can be made that work that fast. Indeed that is pretty slow by modern standards, any major silicon foundry should have no trouble doing it. If you are working with a silicon foundry they should tell you what cell libraries you should be using in your tools to take advantage of their process.

You would then synthesize your design, look at the reports for what paths are the bottlenecks and tweak your design to improve them. You may also decide you need to move to a more expensive process or a faster (but more power hungry) set of libraries.

Remember clock speeds are not just limited by the flip flops but by the combinatorial logic between them. The clock to output delay of the source flip flop, the delay in combinatorial logic, the routing delay and the setup time of the destination flip flop all have to happen between one clock edge and the next.

Note that programmable logic is much slower than dedicated silicon. Getting more than 150MHz or so on programmable logic is hard. It's not so much the flip flops themselves as all the complex routing logic that links everything together in arbitrary ways.

Also input and output become a problem. It is extremely difficult to make IO pins work at those kinds of speeds.

Peter Green
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