Slow clk output (Spartan-6)

Question

I have a design which looks like this:

-controller
--Module1
---SubModule1.1
---SubModule1.2
----SubModule1.2.1
--Module2
---SubModule2.1
---SubModule2.2
---SubModule2.3
---SubModule2.4
--Module3
---SubModule3.1
---SubModule3.2
---SubModule3.3

So I got a top-level module called controller which inherits 3 Modules. Each Module is connected to a FIFO as a Buffer. So the output of Module1 is connected to the Input of FIFO1 and the output of FIFO1 is connected to the input of Module2 and so on.

Now here's my problem. If I run Place & Route with Xilinx ISE it gives me

----------------------------------------------------------------------------------------------------------
Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                          |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP       |         N/A|     9.055ns|     N/A|           0
_IBUF_BUFG                                | HOLD        |     0.411ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP       |         N/A|    18.826ns|     N/A|        5804
_IBUF                                     | HOLD        |     0.131ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Ins | SETUP       |         N/A|     8.537ns|     N/A|           0
t_part1/Inst_A2Precalc/state[2]_GND_274_o | HOLD        |     1.534ns|            |       0|           0
_Mux_639_o                                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Ins | SETUP       |         N/A|     7.946ns|     N/A|           0
t_part1/Inst_A2Precalc/state[2]_GND_306_o | HOLD        |     1.890ns|            |       0|           0
_Mux_703_o                                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Ins | SETUP       |         N/A|     7.966ns|     N/A|           0
t_part1/Inst_A2Precalc/state[2]_GND_338_o | HOLD        |     2.224ns|            |       0|           0
_Mux_767_o                                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Ins | SETUP       |         N/A|     8.252ns|     N/A|           0
t_part1/Inst_A2Precalc/state[2]_GND_370_o | HOLD        |     1.950ns|            |       0|           0
_Mux_831_o                                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------

So clk_IBUF has a Best Case Achievable of 18.826ns which is too slow for my case. Does this mean that the clk needs 18.826 to reach all clocked parts? And how could I possible improve this? And can I somehow look up what exactly causes this?

Tell the tools what speed you need to achieve, then re-synth, P&R again. If there's a target speed (a timing constraint) the tools will try to meet it. If that fails, then you need to look at the design in more detail. — , Dec 10 '15 at 18:33
Sorry, in my suggested edit, I removed the first report line for `clk_IBUF_BUFG`. This line could be of importance because it seems that you used the same clock `clk` twice, before and after the global clock buffer `BUFG`. — Martin Zabel, Dec 10 '15 at 19:01

Martin Zabel · Accepted Answer · 2015-12-10T18:57:30.467

Does this mean that the clk needs 18.826 to reach all clocked parts?

It actually means, that the maximum delay of the combinational path between two FFs driven by that clock (or back to the same FF) is 18.826 ns. This delay is the sum of the clock-output time of the source FF, the delay of the combinational logic, and the setup-time of the destination FF.

And can I somehow look up what exactly causes this?

After P&R the ISE toolchain runs the static timing analyzer. In this report, you will find the path which actually causes the high delay. If the report is almost empty, then you must specify a clock constraint with the desired clock frequency in a UCF file, which must be added to your project. An example clock constraint would be:

NET "clk" TNM_NET = "clk_grp";
TIMESPEC "TS_clk_grp" = PERIOD "clk_grp" 100 MHz HIGH 50%

And how could I possible improve this?

As you already buffered the data-path using FIFOs, take a look at the control path.

A common problem with a chain of FIFOs is, that the last FIFO can stall the entire pipeline when it is full. Same applies to the first one, when it is empty. If the FIFO control signals are not buffered by FFs, then this typically leads to long signal path going through all FIFOs in between. Thus, a lot of LUT stages and routing delay causes a long critical path.

Thanks for the answer. I narrowed it down to one Module which violates the time constrain! I'll have a look into Xilinx Timing Analyzer and get back to you guys in a new post. — nablahero, Dec 11 '15 at 01:37

Slow clk output (Spartan-6)

1 Answers1