Can one tri-state pin drive two SS pins?

Question

This is how i see it;

State H: SS out is High, Deselecting SS 2, turning off Q2 and on Q1, which grounds SS 1, turning it on.

State L: SS out is Low, turning off Q1 and grounds SS 2 through Q2. SS 1 is deselected by R1

State Z: SS out is high impedance. R1&3 keep the SSs high. ARGH EDIT: R4 keeps Q1 off. R6 may keep Q2 off. IDK

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Am I wrong? It's purpose is for when gpio pins are a premium.

It's a 3V3 system.

@TomCarpenter The PNP is an emitter follower in that context. For SSoutput = 0 SS2 = 0+ + Vbe_Q2. — Russell McMahon, Nov 30 '15 at 00:49
@TomCarpenter It's common collector. It's a non-inverting, open drain buffer, if you will — Alexander M, Nov 30 '15 at 00:49
I'm meaning it would give you a logic zero or ~0.7V which may not be low enough for some slaves - I suppose if the device is rated for it I may be ok. — Tom Carpenter, Nov 30 '15 at 00:51
It works, but try increasing `R1` and `R3` - it reduces the current through each transistor thus reducing `Vce`. It'll ensure that the SS pins will be low enough. — CharlieHanson, Nov 30 '15 at 00:55
@CharlieHanson Q2 is Com. Collector. It will hold SS 2 at a steady ~0.65V — Alexander M, Nov 30 '15 at 00:57
@AlexanderM Yes, that will be the lower limit (even lower for a 3906, I have found) but `R3` can spoil that if it's too small. — CharlieHanson, Nov 30 '15 at 01:02

Tom Carpenter · Accepted Answer · 2015-11-30T01:49:17.700

My concern is that the low level produced by the PNP will be just under \$0.7\mathrm{V}\$ because of the required \$V_{be}\$ for the transistor to be on. For \$5\mathrm{V}\$ CMOS, the low level input voltage is usually at most \$0.8\mathrm{V}\$ (for \$3.3\mathrm{V}\$ CMOS it will be a little lower), which means you are right on the edge. Personally I wouldn't be happy to run that close to the edge.

In fact, now that I have had a go simulating the circuit, I'm not convinced it will work as planned when floating. Q2 won't turn off properly unless you add a pull up resistor - but in order to be strong enough to work, it would cause Q1 to turn on.

There is a way I have done this in the past, but it requires two comparators. This isn't too bad as a dual-comparator package is only 8 pins and would take up about the same as your discreet transistors.

Basically the approach is to turn the input into ternary - you have equal pull-up and pull-down resistors so that when floating the input voltage will be about half the power rail.

You then have a comparator for each output. For the first device the comparator is set up so that it outputs a low only when the voltage is less than one third of the power supply. For the second device you output a low when the voltage is above two-thirds of the power supply.

It will require 5 resistors and 1 dual-comparator. The circuit is as follows:

The above can be simulated here. It's simulated for \$5\mathrm{V}\$, but the circuit would be identical for \$3.3\mathrm{V}\$.

Essentially the top comparator will be low only when the input is driven high. The bottom comparator will be low only when the input is driven low. If the input floats, both comparator outputs will be high. This is almost a Ternary to Binary converter circuit, it's not strictly speaking as you need the outputs 01,10,11, whereas ternary would be 00,10(or 01),11, but its essentially the same thing just with one bit inverted (hence the comparator is the other way up).

If the comparators are open-drain, which many are, you will also need a pull-up resistor on each output. This shouldn't cause a problem as you will get a nice strong logic 0.

@AlexanderM - it's actually about the same for 3.3V CMOS having looked it up. See my update on a circuit which will do the job if you are prepared to go for a dual-comparator. — Tom Carpenter, Nov 30 '15 at 01:43

score 1 · Answer 2 · answered Nov 30 '15 at 00:51

As shown you concept will not work as when SSoutput is hi-Z, R1 + R2 will bias Q2base lowish and SS2 out will be at an intermediate voltage. While whether this is seen as high or low will depend on the logic family used, it is not a "clean" solution.

Adding a diode or few at key locations may help.

FWIW: The provision of a Hi-Z output state is not usually seen primarily as a means of expending pin count. Main use is to allow "wired OR" arrangements where various pins can be combined logically. BUT any feature can be used for whatever function that the designer's ingenuity may decide :-).

diode from Q2 Base/SS out junction to R2? – Alexander M Nov 30 '15 at 00:53 — Alexander M, Nov 30 '15 at 00:53

score 1 · Answer 3 · answered Nov 30 '15 at 02:39

It transpires that it's possible with just one PNP transistor. It preys on the larger headroom given for logic-high than logic low.

R1, R3 and R4 are quite delicately balanced to leave SS2 (which is directly connected to SSout) as high as possible while making sure Q1 is turned on when SSout is HiZ. Experimentation in the real world might be necessary, but you may also find that the threshold for logic-high is lower than stated in the datasheet.

With SSout driven high or low, the outputs are driven to 3.3V or <0.02V. I'll leave you to work out which one is which.

Can one tri-state pin drive two SS pins?

3 Answers3