I'm working on a project using a Spartan-6. I created a FIFO with the IP Core Generator (New Source -> IP Core -> FIFO -> Generate). The LOG looks like this
The IP Catalog has been reloaded.
Qt: Untested Windows version 6.2 detected!
INFO:sim:172 - Generating IP...
Resolving generics for 'FIFONineBit'...
Applying external generics to 'FIFONineBit'...
Delivering associated files for 'FIFONineBit'...
Delivering EJava files for 'FIFONineBit'...
Generating implementation netlist for 'FIFONineBit'...
INFO:sim - Pre-processing HDL files for 'FIFONineBit'...
WARNING:sim - BlackBox generator run option '-ifmt' found multiple times.
Only the first occurence is considered.
Running synthesis for 'FIFONineBit'
Running ngcbuild...
Writing VHO instantiation template for 'FIFONineBit'...
Writing VHDL behavioral simulation model for 'FIFONineBit'...
WARNING:sim - Overwriting existing file
C:/Users/Christian/Dropbox/workspace/masterarbeit/VHDL/vhdl_work_in_progress/
DifferentialAttack/ipcore_dir/tmp/_cg/FIFONineBit/doc/fifo_generator_v9_3_vin
fo.html with file from view xilinx_documentation
Delivered 3 files into directory
C:/Users/Christian/Dropbox/workspace/masterarbeit/VHDL/vhdl_work_in_progress/Dif
ferentialAttack/ipcore_dir/tmp/_cg/FIFONineBit
Delivered 1 file into directory
C:/Users/Christian/Dropbox/workspace/masterarbeit/VHDL/vhdl_work_in_progress/Dif
ferentialAttack/ipcore_dir/tmp/_cg/FIFONineBit
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'FIFONineBit'...
Generating metadata file...
Generating ISE project file for 'FIFONineBit'...
ERROR:sim - TclTasksC:project_006: Exception detected while executing [project set].
ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'FIFONineBit'. Failed executing Tcl generator.
Wrote CGP file for project 'FIFONineBit'.
Core Generator create command failed.
I already created the project new all over again but it didn't help. Can someone help here?
Update:
If I create a FIFO with the IP Core Generator in standalone mode (Thanks to Paebbels) it fails while Translating with an error:
ERROR:NgdBuild:604 - logical block 'GEN_FIFO[13].FIFONineBit_I' with type
'FIFONineBit' could not be resolved. A pin name misspelling can cause this, a
missing edif or ngc file, case mismatch between the block name and the edif
or ngc file name, or the misspelling of a type name. Symbol 'FIFONineBit' is
not supported in target 'spartan6'.
UPDATE2:
I did solve this on my own. I added the ipcore_dir directory within the translate process properties to the Macro Search path (-sd switch). That worked out! Thanks for your help!
