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Hello as the questions describes I'd like to know whether it's possible to do this ? Can binary executable code which is executed by a processor core possibly be stored using physical silicon gates ? I understand that a device's OS or user application code can be stored in ROM or EEPROM or in flash memory but is it possible to store using physical silicon gates only ? Similarly can a ROM Boot loader be stored using physical silicon gates instead of ROM or flash memory ?[UPDATE] Can binary code be stored on the same area of the die used to represent the core (CPU) design structures ? So using logic gate transistors but not using combinational logic gate transistors (ROM) and not using floating-gate transistors NAND and NOR logic gates (flash memory) and not using floating-gate MOSFET (EEPROM) ?

VictorM
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  • EEPROM and ROM are usually implemented using silicon gates, so yes. – Robert Stiffler Nov 19 '15 at 07:57
  • It depends on what you call "silicon gates". If silicon gates = AND, OR etc gates then the answer would be no as EEP(ROM)s use dedicated cells for storing the data. EEPROM or Flash memory use special transistors with an extra floating gate. Such transistors are useless for AND and OR gates. These use standard transistors without a floating gate. – Bimpelrekkie Nov 19 '15 at 08:08
  • Hello FakeMoustache. What I mean to say is it possible to use the same silicon integrated circuits design which is used to etch out cpu cores and io design functionalities in a SoC to code a device specific OS or device specific application ? Just to be more clear is it possible to code an embedded OS or application in areas of the die other then in easily distinguishable memory areas such as EEPROM, ROM, flash memory and etc.... ? – JkT Nov 22 '15 at 02:53
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    Yes it can and it is very common. The PlayStation 2 BIOS was stored in a mask ROM IC on the motherboard. When you're making millions of something, the costs start to make sense for something like that (and at the time, firmware upgrade delivery mechanisms were much less sophisticated). – Krunal Desai Dec 25 '15 at 16:47
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    I found the part I was thinking of -- the Macronix MX23L6410A is an example of a mask ROM and is the model used in the PlayStation 2. – Krunal Desai Dec 25 '15 at 18:32
  • @Krunal. Thank you for the response. But my question was asking if binary code could be stored in the same area of the die used to represent the core (CPU) design structures ? So using logic gate transistors but not using combinational logic gate transistors (ROM) and not using floating-gate transistors NAND and NOR logic gates (flash memory) and not using floating-gate MOSFET (EEPROM) ? – VictorM Dec 27 '15 at 05:25
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    nor and nand flash is not the same thing as nor and nand gates gates. flash is a floating gate system like eeprom. nor and nand just a term used the describe the structure of the floating gate cell. – Jasen Слава Україні Dec 27 '15 at 09:00
  • @FakeMoustache. You said the below in quotes. Does this mean that EEPROM and ROM use discrete circuits and are not of type silicon based integrated circuits ? "EEP(ROM)s use dedicated cells for storing the data. EEPROM or Flash memory use special transistors with an extra floating gate." – VictorM Dec 28 '15 at 05:44
  • Today's EEP(ROM)s are **not** discrete circuits, they are integrated circuits. Of course you **could** build something of similar functionality with discrete components but then a decent size ROM would be the size of a car ! :-O Not so practical ! Since indeed EEP(ROM)s need special transistors/structures to store the data **without loosing the data when the IC is not powered** so a special (non-standard) IC manufacturing process is needed so that these transistors, with for example a floating gate, can be made. – Bimpelrekkie Dec 28 '15 at 10:43
  • @FakeMoustache. Another question please ? You said that a non-standard IC process is taken with respect to EEP(ROM)s yes ? Then if this type of memory was embedded right onto the die (of a SoC) could a qualified reverse engineer be able to distinguish this area of the die easily from the other parts of the die such as the process to manufacturer the CPU core (which is made from logic gates transistors integrated circuits) ? Also are MaskROM areas also manufactured nowadays the same way as EEP(ROM) ? Thanks again. – VictorM Dec 29 '15 at 03:34
  • You must understand that any chip (for example a SoC) is made using only **one** production process. So if a SoC needs to contain EEP(ROM) (flash memory) then a production process that supports this must be used for the complete SoC. This makes the SoC slightly more expensive (compared to not having that option). On the die you can indeed usually see the memory areas but it is difficult to say if that would be ROM or RAM. – Bimpelrekkie Dec 29 '15 at 12:09
  • MaskROM is basically ROM which is programmed by the design itself. The data is **hardcoded** in the design. You would only use that if you know you need many millions of that ROM and you are 100% sure you do not need to make any software updates. Not so practical indeed. An EPROM (not erasable!) that you can program only once is more convenient. – Bimpelrekkie Dec 29 '15 at 12:12
  • @FakeMoustache. This is for both (Krunal) of you. I was told by Macronix sales that the MX23L6410A is designed from silicon gate transistors integrated circuits. If this is the case would this area of the die be easily distinguished from the silicon gates transistors used to code the CPU cores? – VictorM Dec 30 '15 at 06:56
  • Uhm, 99.999% of all chips today are made using "silicon gate transistors" that includes all kinds of (EEP)ROMs, the lot. All silicon ! So the sales person told you nothing you could not have known already. But there are some variations needed in how the transistors are build up that makes the suitable for an EEPROM or not. But that is irrelevant to almost everyone. Look at the datasheet of the part how to use it, how it is made is usually a company's secret and irrelevant to the user. – Bimpelrekkie Dec 30 '15 at 12:24
  • The MX23L6410A is a mask ROM, it does not contain a CPU. Maybe you should have a look here: http://zeptobars.ru/en/read/open-microchip-asic-what-inside-II-msp430-pic-z80 This site has some photos of the chip dies (a die is the actual chip), as you can see there are regular and irregular structures to be seen. The most regular structures are the memories like RAM or ROM. They look like a matrix because that is how ROM and RAM are organized. – Bimpelrekkie Dec 30 '15 at 12:29
  • This one is a good example: http://zeptobars.ru/en/read/atmel-avr-at90usb162 Most of the area is taken up by the digital logic which makes the microcontroller itself. The yellow part near the bottom and white/striped area on the bottom left are the memories (that is my guess). – Bimpelrekkie Dec 30 '15 at 12:45

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In fact, there are hard-coded bits of data on many processors and other such devices, even complete bootloaders.

There are many ways to do that, sometimes it's just an array of hardwired shorts to VCC or GND that are selected in a grid, just like the bit-cells in an EEPROM device.

Or sometimes it's a row driver with diodes and pull down or pull up resistors, or a similar trick, where the row driver decodes the address it's given, much like a 3-to-8 decoder, but larger:

Consider this "8 row, 3bit Hardwired rom":

schematic

simulate this circuit – Schematic created using CircuitLab

And since I'm not a chip designer, I'm probably overlooking some details here and there, but I'm quite sure there's a lot of ways this similar trick gets done. In some, or even many, cases they may make a grid with all diodes, or links, present and then laser etch away the paces where they want the opposite bit to come out, for example with unique IDs, where every chip gets lasered an increasing number in a fixed spot in the memory, that will not decay over time like Flash or EEPROM (though the latter has become nearly ageless by now).

Asmyldof
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Executable code is just data, ones and zeros. How to store that ? You need something where you enter the address of the memory location you want to read and at the output the corresponding data appears. Can you make such a thing using standard gates (AND, OR etc.) ? Yes, it is just combinatory logic.

Is that efficient ? No it is not, for it to be efficient you want to use the smallest devices possible. These smallest devices are specially designed to store data and to fit as many as possible on a given area.

If you would use standard logic gates (AND, OR etc) then this would use a lot more area. You would also need to connect them in certain ways to define if a zero or a one is stored.

Bimpelrekkie
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Fusing or anti-fusing is probably the simplest way to store bits in silicon. All it takes in a higher current to blow the fuses which then corresponds to a zero or a one. There's various implementations of fusing which are described in more detail here.

horta
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Yes you can encode binary data in an arrangement of gates.

eg: a collection of and gates and inverters to decode each address into a individual row line, and then combine the row lines as needed with or gates to get the desired data output.

Jasen Слава Україні
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