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I guess the output state of a D-flipflop is unknown upon power up. But what are the chances that it is neither 0 nor 1 but an intermediate state such as VDD/2? The D-flipflop in this question has an output driver inverter.

Bence Kaulics
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Niranjan Kulkarni
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    A follow up question would be, what are the chances that this intermediate state lasts indefinitely? – Niranjan Kulkarni Nov 01 '15 at 19:17
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    If the inputs are driven to valid logic states, the probability that the output will be in an intermediate state is near zero. – user57037 Nov 01 '15 at 19:18
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    Due to the high open-loop gain of a CMOS inverter, even a tiny bit of energy input, e.g. heat, will push it to a valid output. – Ignacio Vazquez-Abrams Nov 01 '15 at 19:30
  • I think for certain input voltage levels(chances are really little) output may be in the state VDD/2. But if the inputs are in TTL level, output will never be VDD/2. It will settle on either VDD-Offset or GND+Offset. – Alper91 Nov 01 '15 at 21:36

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It depends on the design of the DFF. It can also depend on how long it has been since power was previously removed, and the state of the DFF at that time.

Some DFF design have some asymmetry in them that makes it power up preferentially in a particular state.

'Perfectly' symmetric circuits could theoretically power up in an intermediate state, but that would generally not last longer than the typical settling time of the DFF -- because any thermal (or other) noise would basically be amplified by the latch inherent in a DFF and quickly resolve to one or the other state.

Near the equilibrium point, the output voltage will typically diverge exponentially from that value on its way to either rail.

jp314
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