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okay, i'm an old EE that mostly just writes DSP code and dinks around in MATLAB. but once in a while i get to dabble in more concrete things.

and, actually, this TWI-bit-banging code seems to work, it's just that i was examining it (and refactoring it) and came upon something that seems dubious.

i understand that the TWI slave devices does what it does on the rising edge of the clock SCL. the TWI master writes the SDA bit at some setup time before the rising edge of SCL and the slave reads the SDA line at some time after the rising edge of SCL. i also understand open-collector or open-drain.

my question is, does not the master have to make sure a "1" is written to SDA after the last data bit (the LSB) is written and latched, so that the SDA line is in the open-drain state so that when the slave writes either ACK (0) or NACK (1) the master can read it correctly?

it seems to me that if the master writes a 0 to SDA as the LSB (the last data bit) and leaves it in that state, when the master reads the ACK bit, it will always come back as 0 (ACK) even when the slave wants to send a NACK.

currently, in this TWI bit-banging code, they are reading the ACK and saving it in a word somewhere, and i tested it and it never comes out any different than 0 or ACK, but i wonder if something is wrong and a NACK is sent back, we might never know it. these are control-register bytes going to a codec and a lot of those bytes are just zero and those that are not most often have 0 for the LSB. so i am wondering if we're making it impossible for a NACK to be detected.

thanks for any insight from experienced bit-bangers.

robert bristow-johnson
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  • I've seen some I2C slave devices begin driving ACK as soon as the 8th falling edge of SCL, just after the 8th data bit from the master and before the 9th SCL rising edge. But you're right that the master must not drive SDA low during the 9th SCL pulse (at least in master transmit mode). – MarkU Oct 19 '15 at 21:54
  • perhaps i should change "master" to "transmitter" and "slave" to "receiver" in the question. – robert bristow-johnson Oct 19 '15 at 22:02
  • By "TWI" I suspect you mean I2C. Otherwise for an imaginary interface standard, I don't see why it has to be this way. – Fizz Oct 19 '15 at 22:07
  • If you change "master" to "transmitter", that might confuse things further. "Master transmitting" and "master receiving" are different scenarios. – Nick Alexeev Oct 19 '15 at 22:13
  • @RespawnedFluff, yes, it **is** I2C. put that as a tag. for some reason, people get a little excited when i specifically say *"I2C"* for whatever reason the term *"TWI"* was coined. the master device is a ADSP-21479 SHArC and the slave is a AK4954 codec. the thing actually comes up and works and the ACK bit, bad or good, is not read. but i am wondering if a NACK would ever be read from the SDA line. – robert bristow-johnson Oct 19 '15 at 22:22
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    TWI is the name of the trademark free version of I2C http://electronics.stackexchange.com/questions/50915/what-is-difference-between-i2c-and-twi @RespawnedFluff – Passerby Oct 20 '15 at 00:05
  • @Passerby: Someone should fix the wiki tag on that... – Fizz Oct 20 '15 at 00:08
  • @RespawnedFluff just updated it. The tag is a bit redundant, at the same time it's not. Not sure if it should just be made a synonym. To meta... – Passerby Oct 20 '15 at 00:27
  • @RespawnedFluff ahhhhh http://meta.electronics.stackexchange.com/questions/3388/tag-synonyms-suggestions about that. See this meta and answers. I forgot all about it – Passerby Oct 20 '15 at 00:33

2 Answers2

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my question is, does not the master have to make sure a "1" is written to SDA after the last data bit (the LSB) is written and latched, so that the SDA line is in the open-drain state so that when the slave writes either ACK (0) or NACK (1) the master can read it correctly?

Yes, and no. The Master is supposed to release the line, allowing it to default to the open state, which is pulled up by the i2c pull-up resistors. This is effectively the same as writing a 1, but is not referred as such, because that is a confusing way to state it. Typically, SDA is released by putting the pin in a High-Z input mode.

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Having wrote a bit-banged i2c library myself, I'd suggest a way of testing your code. Attempt to write to a nonexistent slave address. If you get back a ACK (0), then something is not right with your code. A nonexistent slave cannot pull SDA low, so you should always get a NACK (1) when talking to a wrong address.

Passerby
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  • *"This is effectively the same as writing a 1, but is not referred as such, because that is a confusing way to state it."*, well, when you're writing code and your choice is writing "0" or "1" and the output bit is left in that state until it's changed. your test suggestion is right on. i'm gonna check that out. (it's all academic now, i just discovered from reading the 21479 hardware reference manual that there is a built-in TWI interface feature. so this is likely legacy code (for SHArCs that didn't have a built-in TWI) that i am looking at. – robert bristow-johnson Oct 20 '15 at 23:01
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TWI is the same as I2C but avoids copyright issues, Philips (now NXP) owns the copyright. (I2C specification)

Be careful about using the Master and Slave terminology, much of the protocol is the same for master and slave and the differences depend upon whether the unit is transmitting or receiving.

The transmitter drives the SDA line while the clock is low and leaves it stable while the clock is high - again it is the same whether the master or slave is doing it. The only place where this rule is violated is in the generation of the stop and start bits that are done by the master.

The ACK may be driven low by the receiving unit, regardless whether it is the master or slave. Following the slave address it means the address is recognized, following a write it means that the slave has accepted the data and can receive more. If the address is not recognized or it cannot accept more data the line is left to be pulled high by the pull-up (it is not driven high!). After a read it is the master that ACKS or NACKS to indicate whether the transaction is complete as the master is the receiver in that instance.

The transmitting unit obviously has to ensure that SDA is not driven for the ninth bit, or the receiving unit will not be able to pull the line low or not to indicate its status.

Kevin White
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  • i agree with you about the master/slave thing but sounds like @NickAlexeev might not. that's why i mentioned i might should change it. by *"The transmitting unit obviously has to ensure that SDA is unasserted for the ninth bit, or the receiving unit will not be able to pull the line low to indicate its status."* by *"unasserted"* do you mean "0" or "1"?? or do you mean "open-drain" vs. whatever is opposite? because "open-drain" means "1" (and usually i think that means "asserted"). and the problem for the receiving unit is not that it can't pull the line low, but that it can't send a NACK. – robert bristow-johnson Oct 20 '15 at 22:56
  • By unasserted I mean that the device is not driving the SDA line. Since it is an open collect/drain bus it will not be driven to a 1. The pull up will do that of nobody else is driving it. – Kevin White Oct 21 '15 at 01:28
  • I've changed the wording to make it clearer. – Kevin White Oct 21 '15 at 01:31