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I see many circuits use this topology Clock Generator

Why dont we use just only one inverter like this: Inverter

Thanks very much!

Earthgod
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  • I think it has to do with the delay introduced by the inverter. The D-line gets slightly more time to settle with respect to CLK before its logic level is clocked into the flip flop. On top of that the clock pulse is being reshaped to a square, shaving off any ringing introduced by long leads. – jippie Oct 13 '15 at 04:32
  • I agree with Jippie. It's likely just introducing enough delay in the inverted buffer to allow more time for QM to setup and hold before being clocked in. – Kurt E. Clothier Oct 13 '15 at 04:39
  • I think @IgnacioVazquez-Abrams has a valid point too. – jippie Oct 13 '15 at 04:40
  • I think this is a good question and does not deserve to be closed. – Michael Karas Oct 13 '15 at 05:02
  • Even good questions deserve to be closed if they their answer has already been given on another question. – Wouter van Ooijen Oct 13 '15 at 05:36
  • Sorry. I already searched, but maybe the key didnot match. I also dont want to spend time to ask another question where another similar question has been answered. Sorry again. – Earthgod Oct 13 '15 at 06:19
  • No worries. There are many ways of asking the same question, and it's impossible to search for all the possible ways of asking it. – Ignacio Vazquez-Abrams Oct 13 '15 at 09:14
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    @IgnacioVazquez-Abrams I disagree that this is a duplicate, or rather that the linked question answer applies. In the link, the double inverter is used to buffer the input and reduce loading on the source. I believe in this case that it is done to provide an output transition on the positive clock edge. – WhatRoughBeast Oct 13 '15 at 14:30

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