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I am tasked with the issue of driving an IC that wants 5V input signals from an FPGA (3.3V outputs). Now, the most daunting part of it is the slew-rate requirements, with rise time \$t_r = 1.5 \text{ns},\$ hold time \$t_h = 3.5 \text{ns}\$, fall time \$t_f = 1.5 \text{ns}\$ and rest time \$t_l = 12 \text{ns}.\$ "High" is more than 4.75 V (5.0V typ) and "low" is less than 0.4 V.

If you add up the numbers, this corresponds to a period \$T=18.5 \text{ns}\$, or frequency of \$f=54.0 \text{MHz}\$. But the slew rate is

$$sr = \frac{5\text{V}}{1.5\text{ns}} = 3.333 \frac{\text{V}}{\text{ns}} = 3,333\;\text{V/$\mu$S}.$$

The Texas Instruments LMH6738 seems to be my only choice, so I can solve my problem by amplifying the signal (\$A=\frac{5}{3.3} =1.5\$). But before going that way I wondered if there were other options. After all, this is still a digital signal so I might not need to use it. A 5V digital signal at frequency $$f = \frac{1}{1.5\;\text{ns}} = 666 \text{MHz},$$ or higher would do just fine. But as far as I know, there's few logic chips working with 5V logic at those speeds.

So, any recommendations?

Pål-Kristian Engstad
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  • Rise and fall times are generally much faster than the design clock period, so you can generally get away with using a chip designed for a significantly lower frequency. Anyway, how many signals do you need to level translate, and do you need to go both ways or only from 3.3 to 5v? – alex.forencich Aug 31 '15 at 19:12
  • Yes, that's an idea. I could probably get by with a 4.625 ns clock, sending (HIGH, LOW, LOW, LOW) repeatedly. That would require a 216 MHz signal @ 5V. – Pål-Kristian Engstad Aug 31 '15 at 20:25

4 Answers4

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A opamp in this application makes no sense.

It seems you want to do ordinary digital signal level translation, so get a level translator chip. Even a TTL logic chip run from 5 V will work since 3.3 V is well above the guaranteed logic high level for a TTL input.

Olin Lathrop
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  • That would be true if the chip in question is a TTL logic chip. This one isn't. The requirements I've listed are the ones I have to meet. For instance, a 3.3 V swing would not even trigger the chip on the receiving end. It needs to be above 4.75V for a minimum of 3.5 msec, and that pulse needs to happen within the first 6.5 msecs of an 18.5 msec cycle. – Pål-Kristian Engstad Aug 31 '15 at 21:22
  • @Pål: Like I said, a TTL-input logic chip can function as a level translator from 3.3 V to 5 V. That can be convenient if you have unused gates, or some additional logic is beneficial. The output will be 0-5 V and compatible with 5 V logic. – Olin Lathrop Aug 31 '15 at 21:48
  • Ah, I see what you mean. E.g., just use an unused NAND or NOT chip. Thanks! – Pål-Kristian Engstad Aug 31 '15 at 23:44
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You could utilize an Analog Devices AD8003 (slew rate over 4,000 V/us at gain of 2).

However, I would also consider a logic level shifter. TI and Maxim make some, but I don't know if they have one specific for 3.3 to 5. One advantage is that they are 2-way in case that becomes required at some point.

Also note that it may not be critical to hold the sharp transition depending upon how often the signal changes states and when it is clocked into the other IC. Just because the FPGA can provide such a high speed transition does not guarantee that it is required. For example, if the signal is clocked out at only 10 Mbps and clocked out of phase from the transition, you would have 50 ns to achieve the level.

MikeP
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Don't bother with an op-amp if it's just for a digital signal. You can get gobs and gobs of digital level translator chips: http://www.digikey.com/product-search/en/integrated-circuits-ics/logic-translators/2556437 .

74LVC8T245 might be a good option, it's spec'd at being able to support 420 Mbit/sec when translating 3.3v to 5v.

alex.forencich
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  • The 74LVC8T245 has a slew rate 10 ns/V, or 50 ns for 5V, which clearly is too slow. – Pål-Kristian Engstad Aug 31 '15 at 19:50
  • Ah, good point, that 420 Mbit/sec is probably assuming parallel transfer on all 8 channels, or 53 Mbit/sec per channel, which might be too slow. There are probably faster chips, though. – alex.forencich Aug 31 '15 at 20:38
  • It's really hard to say, though. The datasheet does not list any really definitive output slew rate information. Perhaps it would be a good idea to get some samples and test it? – alex.forencich Aug 31 '15 at 20:39
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A high speed translator might be better than an opamp.

This is a selector on the TI web site - Voltage Translator Selector

One possible device is - LVCT145 datasheet it claims operation up to >400mbps.

This question was asked previously (Is there any bidirectional 5v-3.3v level shifter?) and answered by Lazarus

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Kevin White
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  • Thanks, but the LVCT145 is also too slow (10 nS/V). – Pål-Kristian Engstad Aug 31 '15 at 19:57
  • @Pål-KristianEngstad What about your application has you so hung up on slew rate? It seems like you're trying to take a cannon to a pillow fight, and that is going to significantly reduce your options. – Matt Young Aug 31 '15 at 20:14
  • My IC seems to have some very specific requirements, and I have to meet those specs in order for the chip to function properly. – Pål-Kristian Engstad Aug 31 '15 at 20:17
  • @Pål-KristianEngstad - you're not reading the data sheet correctly. That 10ns/v is the slowest INPUT slew rate that it is recommended. It is not the the output slew rate, that is not in the data sheet. However the propagation delay is only 3.9ns when giving 5V swing. It is probably better than 1ns/V. – Kevin White Aug 31 '15 at 20:20
  • @KevinWhite Ah! Good to know. I will reread the data sheet! – Pål-Kristian Engstad Aug 31 '15 at 20:26