how to interpret the RTL report after synthesis in Xilinx?

Question

I did verilog code of a circuit. It was simulating well and giving output correct after Simulation. Now i did synthesis, the RTL schematic after synthesis showing some green and red box. Is it indicating any kind of error? Please give any comment to clear this confusion. Thank you.

Asking about the red and green boxes which i highlight using white color lines.

score 1 · Accepted Answer · answered Jul 19 '15 at 11:31

1

There is no error.

Green Box: start of a wire.
Red Box: end of a wire.

I don't know why ISE's RTL viewer shows these boxes. Inputs and outputs are defined by the right and left side of sub-schematic...

answered Jul 19 '15 at 11:31

Paebbels

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I presume they are shown on the net you have selected really just to highlight connections - its far easier to spot a big box when zoomed out in a big schematic. – Tom Carpenter Jul 19 '15 at 12:39

how to interpret the RTL report after synthesis in Xilinx?

1 Answers1