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Can someone shed light on what this SystemVerilog code should do:

typedef struct {
 logic [15:0] a;
 logic [15:0] b;
 logic [15:0] c;
} my_struct;

localparam my_struct s = '{default:'1, c:0};

Is this legal? I can't quite figure out the spec well enough to tell. This doesn't work right with Vivado, and I'm not sure why.

This works:

localparam my_struct s = '{default:0, c:'1};

Thanks, Nachum

nachum
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2 Answers2

8

Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns

my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000};
my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF};

Your version Vivado might not have implemented the default:'1 feature yet or it could be a bug in the simulator. Try to run the latest version.

Try default:16'hFFFF or default:-1 as possible work around.

Greg
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2

One way to define complex structs can be explained with an example.

Lets be the following struct, which is a struct of integer arrays and a sub-struct called: AXI_PRM_STRCT

//local constant
localparam int MAX_AXI_INTERCONNECT_PORTS=5;//maximun number of input or output ports, the max_input+max_output=10 ports for interconnect
//The sub-struct

typedef struct {
    int VERSION    = 3;   //Default value, this is overwritten in top package
    int AXI_LEN_BW = 4;//Default value, this is overwritten in top package
    int AWUSER_BW  = 0;
    int WUSER_BW   = 0;
    int BUSER_BW   = 0;
    int ARUSER_BW  = 0;
    int RUSER_BW   = 0;
} axi_extend_param_struct_type;   

//the complex/compound struct
typedef struct {
    //string AXI_INTERFACE_STRG_ID="";
    int N_PORTS_USED=1;
    int AXI_ADDRWIDTH[MAX_AXI_INTERCONNECT_PORTS] = '{MAX_AXI_INTERCONNECT_PORTS{32}};//Array values all the same
    int AXI_DATAWIDTH[MAX_AXI_INTERCONNECT_PORTS] = '{MAX_AXI_INTERCONNECT_PORTS{32}};//Array values all the same
    int AXI_ID_BW[MAX_AXI_INTERCONNECT_PORTS]     = '{MAX_AXI_INTERCONNECT_PORTS{1}};//Array values all the same
    axi_extend_param_struct_type     AXI_PRM_STRCT [MAX_AXI_INTERCONNECT_PORTS];
} axi_interconnect_struct_type;

That complex struct can be initialized with literals in the following way:

localparam axi_extend_param_struct_type   AXI_PRM_STRCT             = '{VERSION:3, AXI_LEN_BW:8, AWUSER_BW:32, WUSER_BW:32, BUSER_BW:32, ARUSER_BW:32, RUSER_BW:32};  
localparam axi_interconnect_struct_type   INPUT_MAST_INTF_STRCT_ARR = '{N_PORTS_USED:2, AXI_ADDRWIDTH:'{MAX_AXI_INTERCONNECT_PORTS{32}}, AXI_DATAWIDTH:'{MAX_AXI_INTERCONNECT_PORTS{32}}, AXI_ID_BW:'{MAX_AXI_INTERCONNECT_PORTS{4}}, AXI_PRM_STRCT:'{MAX_AXI_INTERCONNECT_PORTS{AXI_PRM_STRCT}}};

There is other ways to init with literals 

localparam axi_interconnect_struct_type INPUT_MAST_INTF_STRCT_ARR = '{N_PORTS_USED:2, AXI_ADDRWIDTH:'{32,32,32,32,32}, AXI_DATAWIDTH:'{32,32,32,32,32}, AXI_ID_BW:'{4,4,4,4,4}, AXI_PRM_STRCT:'{AXI_PRM_STRCT,AXI_PRM_STRCT,AXI_PRM_STRCT,AXI_PRM_STRCT,AXI_PRM_STRCT}};
Joniale
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