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Xilinx FPGAs are capable of using LUTs as memory elements. The can be used as ROM, RAM and Shift Register (SRL).

New Xilinx devices use 6-input LUTs, which gives 64x1 bit for RAMs/ROMs, but only 32 bit for SRLs.

Why are SRLs restricted to 2^5 bits?

I'm not aware of any explanation in the official docs.

Paebbels
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2 Answers2

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I believe this is due to the fact that the LUTs on the Spartan 6 are internally constructed as a 5 input, 2 output LUT followed by a bypassable mux.

Now, why you can't make a 2 bit wide, 32 bit long shift register in a single LUT is a good question. Seems like that should be possible, and then it should be possible to loop the output of one side back around to the other side to get a 64 bit shift register in a single LUT. You'd have to ask Xilinx why they don't support that.

alex.forencich
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I don't have an answer, as I don't know the internal details of Xilinx slices. I do have some pointers.

First, you can't save data in a LUT6. You can only save data in registers (which are numbered 2/LUT6) and distributed RAM/blockRAM. Which somewhat annul your LUT6 = 64 bits assumption.

Distributed RAM and shift registers are somewhat unrelated to LUT6 primitives. If you look at the Spartan-6 Configuration Logic Blocks User Guide, you will see that there are 3 types of slices on that architecture:

  1. Normal slice, having only LUT6 (they do have other things, just nothing relevant to this discussion).
  2. SLICEL, which have LUT6 and fast-carry logic blocks.
  3. SLICEM, which have what SLICEL have, plus distributed RAM.

Shift registers (and distributed RAM) are only available on SLICEM CLBs, which means they need the distributed RAM block as well as the LUT6. Xilinx doesn't gives details on the RAM block, but we know from documentation that a LUT6+RAM can implement a 64x1 bit single port distributed RAM or a SRL32.

A VLSI guru could probably deduce what the internal RAM's details are, but I find reasonable that:

  • 1 LUT6 + 1 RAM block = SRL32
  • 1 LUT6 + 1 RAM block = 64x1b single port RAM
  • 2 LUT6s + 2 RAM blocks = 64x1b simple dual port RAM

As a shift registers is probably implemented as 32 bits dual-port RAMs with specific controls provided by the LUT6.

Jonathan Drolet
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  • My statement LUT6 is used as memory is correct :). It's stated in the CLB manual. Xilinx uses the configuration port of a LUT to allow user access to the stored LUT value. If you use a LUT as RAM it simply means to use the inputs A0 to A5 as address. The therm SliceL/M means that not all CLBs offers this feature (M -> it's available). If you look into the CLB guide, you'll that a LUT can be clocked (shift clock). – Paebbels May 22 '15 at 07:18
  • If you write a 3 bit shift reg in VHDL you will see that ISE generates a SRL16 of 2 bits snd a D-FF. The LUT inputs are used as tap-address. It's possible to implement LUT-RAM based fifos that use only 1 read counter (tap pointer). The fifo write is just a SRL shift in operation. The primitives LUT, RAMxxSy, SRL, ROMxxSy are mapped to the same hardware, just with other control logic enabled. – Paebbels May 22 '15 at 07:26
  • Your linked Spartan6 CLB doc shows these features on page 9. The 4 left most blocks are LUTs which can be configured in many ways (square bullets). You can also see the clk and we inputs. A1 to A6 is uses as write address for LUTs A..D. the normal inputs A1/B1/C1/D1..A6/../D6 are used as read address. There is a dedicated shift route from LUT to LUT di1/di2 -> mc31. Page 17 -> RAM example. – Paebbels May 22 '15 at 07:49
  • You are right. I can only guess for the 32 bits limitation, but still, Xilinx's primitive allow usage of the 64 memory location only on single port configuration (shift register is a special-case dual port). The 64 dual-port memory requires 2 LUTM. – Jonathan Drolet May 22 '15 at 13:42