Poor clock output from Spartan6 FPGA

Question

I am using the LX9 Microboard from AVNET with the Spartan 6 PFPGA. I implement SPI to read from an ADC (ADS7822). I was getting wrong sampled values. When I ched the signals with an oscilloscope, it was not as I expected.

FPGA Clock (system): 100 MHz Divider: 32 SPI Clock (output): 3.125 MHz

So I expect, a 320 ns cycle with 160 ns HIGH time and 160 ns LOW time. From the Simulation I get exactly what i expect. But using an oscilloscope at the PMOD output, I get a clock signal thats not too satisfactory. Also from the ADC datasheet (Pg. 10) the minimum high or low time should be 125 ns when working above 4.74 Vcc. Vcc in my case is 5V.

The high time is 132 ns at 3V level (HIGH) and and 144 ns at 0.8V level (LOW). The clock duration converges at 3.2V level. The expected time is 160 ns and I don't find any reason for the poor clock output.

Below diagram is a screen print of the oscilloscope.

enter image description here

Blue line: CLK Redline: CS

The reason I mark the values at 3V and 0.8V is as per theADC datasheet (Pg. 4) the Vih is from 3 to 5.5V and Vil is from -0.3 to 0.8V.

Please suggest a possible reason for the poor output from the FPGA and how do I improve the clock output?

What specifically is it that appears to be wrong - is the frequency incorrect? Also, what oscope are you using? — Andy aka, May 11 '15 at 11:37
The output doesn't seem bad. It's probably better in reality than your scope is showing, since the probe is loading the line. What you should check is the period -- measure the distance between two consecutive rising edges. — avakar, May 11 '15 at 11:39
@avakar I understand. But at what point (voltage level) should I measure the distance. Ichoose 3V and 0.8 V for HIGH and LOW. The low and high time also matters. — dDebug, May 11 '15 at 11:43
Your measurement is not correct. The duty cycle is measured at 50% (=Vdd/2). So measure again at 1.65 Volt, if Vdd is 3.3V. — Paebbels, May 11 '15 at 11:43
@Paebbels At 1.65V I get proper values (320ns, i.e. 3.125MHz). But doesn't the time for HIGh and LOW a matter for the ADC? — dDebug, May 11 '15 at 11:47
@dDebug, it doesn't matter, the *rising* edges should have the same distance at every level. — avakar, May 11 '15 at 11:48
@dDebug, the rise/fall times do matter sometimes, but in this case they likely don't. And also, your oscope probes are skewing the results. — avakar, May 11 '15 at 11:50
Ok, thanks for the suggestion.I got my doubts cleared. I think avakar and Paebbels had answered, but its in comment and no answer to mark as accepted. Do you guys like to put it in an answer. Then we have a question solved. — dDebug, May 11 '15 at 11:51
@dDebug No, the 'real' high and low time (above 90% of Vdd is high / below 10 % is low) does not matter. If a circuit has special requirements for the clock or data signal, it defines rising and falling time. E.g. \$t_{LH}\$ from low (10%) to high (90%) should be less than 5 ns. So the circuit can be sure that the signal is risen or fallen after a predefined time and the signal can be sampled by the input logic. — Paebbels, May 11 '15 at 12:18
@Paebbels That was a very detailed answer.Thanks your very much for clearing the doubt. — dDebug, May 11 '15 at 12:50

score 6 · Accepted Answer · answered May 11 '15 at 14:14

Your measurement is not correct.

The duty cycle is measured at 50% (\$\frac{1}{2}V_{dd}\$). So measure again at 1.65 Volt, if \$V_{dd}\$ is 3.3V.

The 'real' high and low times:
- above 90% of \$V_{dd}\$ is high
- below 10 % of \$V_{dd}\$ is low
does not matter. If a circuit has special requirements for the clock or data signal, it defines rising and falling time.

Example: \$t_{LH} \le 5\,ns\$
Rise time from low to high (10% to 90%) should be less than 5 ns.

So the circuit can be sure that the signal is risen or fallen after a predefined time and the signal can be sampled by the input logic.

Poor clock output from Spartan6 FPGA

1 Answers1