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I am getting a warning in bitgen like:

This design is using one or more 9k block RAMs(RAMB8BWER). 9k block RAM data, both user defined and default requires a special bit format.

Is it a critical warning or can I proceed with dumping the bitfile onto the FPGA?

Qiu
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Sai Gautam
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1 Answers1

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The warning you are seeing is most likely

WARNING:PhysDesignFules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and default,
may be incorrect and should not be used. For more information, please
reference Xilinx Answer 39999.

I just got this warning myself a couple of days ago and looked in to it. See http://www.xilinx.com/support/answers/39999.html . Basically, if you are using a newer version of ISE (13.2 or newer, 14.7 is the latest) and you are not using bitstream encryption, you can ignore the warning.

You really gotta love this sort of bug: they screw up the design, find the issue, and then just change the spec. "That's not a bug, that's a feature!"

alex.forencich
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  • Thanks....I was wondering if some other part of my design was triggering this warning. Because if I comment out DFT module of the project, this warning disappears and the output is as expected. The DFT module uses a sine table block RAM – Sai Gautam May 11 '15 at 08:30