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I have designed a Costas Loop for carrier synchronization in MATLAB, here is my code:

% Siraj Muhammad
% 25/3/2015
% BPSK Demodulator
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

load RRC.mat

fc = 0.0500001;
phase_offset = pi/7;

N = length(rf_signal);
bb = zeros(1, N);
bb_f = zeros(1, N);
I_f = zeros(1, N);
Q_f = zeros(1, N);
I_r = zeros(1, N);
Q_r = zeros(1, N);
error = zeros(1, N);
PhErr = zeros(1, N);
error_integral = zeros(1, N);

% Loop Filter Coefficients
C1 = 2^2;
C2 = 1/2^8;

for i = 2:N
    % Downconverting to Baseband
    bb(i) = rf_signal(i).*exp(j*2*pi*fc*i+j*phase_offset).*exp(-j*PhErr(i-1));

    % Filtering
    bb_f = filter(RRC, bb(1:i));
    I_f = real(bb_f);
    Q_f = imag(bb_f);

    % Slicing
    I_d = sign(I_f(i));
    Q_d = sign(Q_f(i));

    % Error
    error(i) = I_d.*Q_f(i);

    % Loop Filter
    error_integral(i) = error(i).*C1 + error_integral(i-1);
    PhErr(i) = (error(i).*C2 + error_integral(i))/2^5;
end

figure; subplot 321; plot(real(bb)); title('I Channel')
subplot 322; plot(imag(bb)); title('Q Channel')
subplot 323; plot(I_f); title('I Channel Filter')
subplot 324; plot(Q_f); title('Q Channel Filter')
subplot 325; plot(error); title('Phase Error');
subplot 326; plot(PhErr); title('Loop Filter');

rf_signal is generated in another MATLAB script that produces BPSK signal. Simulation in MATLAB shows good results, loop tracks phase and frequency and locks on them.

Costas Loop MATLAB Simulation

After I verified the design, I implemented it in VHDL using some Altera MegaCores. However, ModelSim simulation doesn't show the expected result. Loop seems to oscillate rather than locking, even though the loop is closed.

ModelSim Simulation

And this is the loop filter's output, you can see how it is oscillating.

Loop Filter

I checked all signals widths and made sure that they do not overflow. When I open the loop in MATLAB and ModelSim, I get the same loop filter output.

Open Costas Loop - MATLAB

Open Costas Loop - ModelSim

They are opposite because data is modulated with cosine in MATLAB and sine in ModelSim. Problem is when the loop is closed.

Any advice would be appreciated.

Siraj Muhammad
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  • The only thing that I can think of offhand is a possible issue with delay. If the various signal processing modules are pipelined, the extra clock cycles of delay could be causing oscillations. – alex.forencich Mar 31 '15 at 21:23
  • *"I implemented it in VHDL using some Altera MegaCores."* -- Without knowing anything about that implementation, how could we possibly determine whether it is an accurate translation of the Matlab model? You have already pointed out one major difference between the two. – Dave Tweed Mar 31 '15 at 21:33
  • @alex.forencish I had this idea, and I used the CICs output to calculate the phase error instead of the RRCs output since the latter suffer from a longer delay. But nothing changed, same result. – Siraj Muhammad Apr 01 '15 at 06:40
  • @DaveTweed You can be sure of it. The results when the loop is open can give you an initial idea. However, I doubt Altera's NCO to be causing the problem, since everything is straightforward... multiplications and additions! – Siraj Muhammad Apr 01 '15 at 06:43
  • If you're so sure that the VHDL matches the Matlab, then why are you here? What's your actual question? FWIW, the waveform of the "Loop Filter" signal in your ModelSim simulation is not really oscillation; it looks exactly like the first part of the lock-up transient in a PLL -- in other words, I think it *IS* working, but you just haven't allowed it to run long enough to complete the process. – Dave Tweed Apr 01 '15 at 11:13
  • Thanks Dave, I'll see what I can do. I changed the NCO to pure VHDL DDS I wrote... initial results indicate a possible success. – Siraj Muhammad Apr 01 '15 at 13:20

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