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From what I have been reading, the input stages to BJT TTL logic gates are emitter terminals of transistors. As such, when the input to these gates is logic low the base-emitter junction of these input transistors will be forward biased and source current (sinking into the first stage). Further, this is the reason we find that tables similar to the following in some datasheets :

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I am referring to the polarity of the current when considering polarity of logic levels. Specifically, the fact that maximum operating condition of -800uA for a logic level high is non-intuitive. Should it not be that when a gate is driven LOW the second-stage gate actually sink current into the first-stage? That is, shouldn't sinking current (logic low output state) be negative and sourcing current (logic high) be positive?

My concern is how this maximum current sink metric is related to the maximum current that may be sourced when the output of a gate is driven to a logic high state. Specifically, I had the following condition as of late:

I was recently designing a circuit that used a 74LS163 counter where the outputs were fed into some second stage logic. However, I placed some LED indicators temporarily at counter output while prototyping this circuit in order to see what the count value was at a given time. I used series resistances of 1k to severely limit the current in order to not load the output driver too much, but saw a very significant output voltage drop anyway.

Specifically, The LED I was using had a forward voltage of 2.5V. The nominal, unloaded, output of the counter was 4.5V. With the 1k series resistance we find that a mere 2mA would be drawn to drive the LED. I found that the LED indeed was dimly lit, but the output voltage dropped 1V to 3.45V despite such low current demand.

tl;dr : This led me here. The maximum current when the output is driven high is given as a maximum sinking current, but obviously the counter sources some level of current at this voltage. How do these values shown in the datasheet relate to sourcing current at logic HIGH and sinking current and LOGIC low?

sherrellbc
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2 Answers2

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The convention is that when the gate output is sourcing current it is given a negative sign and when it is sinking it is given a positive sign.

True TTL gates (such as 7400) actually did require current to bring the inputs high as the reverse Hfe of the multi-emitter transistor is not zero. This current is typically shown as 40uA.

Later devices such as LSTTL typically use multiple diodes at the input and require much less current.

m.Alin
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Kevin White
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I am referring to the polarity of the current when considering polarity of logic levels. Specifically, the fact that maximum operating condition of -800uA for a logic level high is non-intuitive.

This is just the passive sign convention for current in a circuit branch. In this convention current in to the positive terminal of a branch is positive current. With this convention then when you calculate power as \$P=IV\$ if \$P>0\$ then power is being delivered to the branch, and if \$P<0\$ then the branch is delivering power to the rest of the circuit.

The Photon
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  • Yes, of course. My question was more specifically why the device will sink current (-800uA) with an output logic level high. Intuition tells you that with a logic high output that the device would be sourcing current to the next stage, not sinking from it. – sherrellbc Apr 08 '15 at 14:32
  • In this case, considering the PSC, would it not be then that with -800uA leaving the voltage source (output of the logic device) we could say that we rather have positive 800uA entering the source? From here, 800uA*VHIGH is a positive value and therefore indicates the source is consuming energy rather than delivering it. EDIT: Page 33 [here](http://www.ti.com/lit/an/szza036b/szza036b.pdf) explains it perfectly. Thank you! – sherrellbc Apr 08 '15 at 15:26
  • @sherrellbc, "-800 uA" means the pin is sourcing 800 uA. This is the *passive sign convention*. Read the Wiki article I linked in my answer to understand why this convention is used. – The Photon Apr 08 '15 at 15:40
  • Yes, I understand what it means. I was confused on whether it meant -800uA into the source or -800uA out of the source. Only the former of the two conforms to the passive sign convention. After reading page 33 of the link I posted in my last comment was it explicitly stated. I wrote above "if .. -800uA leaving the source .. ", which is not correct and why my results were inconsistent with the PSC. – sherrellbc Apr 08 '15 at 15:46
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    @sherrellbc, Just above you talked about "-800uA leaving the source". This is incorrect. The passive sign convention says that current is always specified entering the designated positive pin. So a -800 uA current means 800 uA being sourced by the component, and the datasheet is specifying the maximum current sourced (not sunk) when the output is high. – The Photon Apr 08 '15 at 15:59
  • Note that not all IC makers use the passive sign convention when specifying their outputs, but TI (which looks like where you got your example) is one that does. – The Photon Apr 08 '15 at 16:01