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How can I find Gate Delay for bit 1 of the sum by a 4-bit look-ahead carry adder?

enter image description here

Wouter van Ooijen
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Rohit Gulabwani
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  • Take the circuit diagram an find the logest path from that input to an output. – Wouter van Ooijen Feb 24 '15 at 16:50
  • https://www.google.co.in/search?q=gate+delay+for+4+bit+carry+look+ahead+adder&es_sm=93&biw=1366&bih=667&source=lnms&tbm=isch&sa=X&ei=NqvsVJGFLJLc7QbIzYCwCw&ved=0CAYQ_AUoAQ#tbm=isch&q=carry+look+ahead+adder+schematic&imgdii=_&imgrc=m095CQXBVYyzCM%253A%3BD8JK-o2va1GixM%3Bhttp%253A%252F%252Fupload.wikimedia.org%252Fwikipedia%252Fcommons%252Fthumb%252F0%252F04%252F4-bit_carry_lookahead_adder.svg%252F2000px-4-bit_carry_lookahead_adder.svg.png%3Bhttp%253A%252F%252Fen.wikipedia.org%252Fwiki%252FAdder_(electronics)%3B2000%3B1200 This is the diagram but i am not able to figure out can you explain me? – Rohit Gulabwani Feb 24 '15 at 16:58
  • I have seen the diagram C1 is found after 3 gate delays and then to find S1 1 more delay will add. So the answer to this will be 4 gate delays. Am i right? – Rohit Gulabwani Feb 24 '15 at 17:11
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    I dunno, because you did not show (liked to) a gate-level circuit of the adder you refer to. Without such a circuit the question can't be answered. (But I very much doubt 4 is the correct answer.) – Wouter van Ooijen Feb 24 '15 at 17:56
  • @WoutervanOoijen I sent the link in the comment. The first full adder will give C1 so find C1 the first adder will take three delays and then as the second full adder gets C1 it will find S1 in one delay so the net delay will be 3+1=4. If you know this then please correct me. – Rohit Gulabwani Feb 24 '15 at 18:01
  • I have edited the picture you linked to into your question. It is at block-level, not at gate level, so it can't be used to count gate delays. – Wouter van Ooijen Feb 25 '15 at 08:50

1 Answers1

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You want to take the internal logic for a 4-bit adder with look-ahead carry, such as the 74HC283:

enter image description here

and then count up the longest possible gate delay for S2, or bit 1 (I get 6).

tcrosley
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  • sir i need to find for S2 from your diagram as LSB in my case is zero. – Rohit Gulabwani Feb 24 '15 at 18:23
  • Thank You sir i think i got it. So the final answer for S2 will be 6. – Rohit Gulabwani Feb 24 '15 at 18:27
  • The maximum path from A2 or B2 to S2 is 5 (I was using S3 before, which was 6). The maximum from A1 or B1 to S2 is 6. – tcrosley Feb 24 '15 at 18:28
  • So what is the one i need to consider if i am asked the question gate delays occur in computing bit1 of the sum by a 4-bit look-ahead carry adder?LSB being 0. – Rohit Gulabwani Feb 24 '15 at 18:30
  • If you are referring to input bit 1 (A2/B2 in the diagram), then answer is 6, from A2/B2 to S3. If you are talking about output bit 1 (S2 in the diagram), then you are also talking maximum of 6 (A1/B1 to S2). If you are talking both input bit 1 (A2/B2) to output bit 1 (S2), the answer is 5. – tcrosley Feb 24 '15 at 18:36
  • I am confused sir my question is to find gate delays occur in computing bit1 of the sum by a 4-bit look-ahead carry adder? (bit0 is the LSB) so for that i guess i am getting 6. Am i correct? – Rohit Gulabwani Feb 24 '15 at 18:43
  • @RohitGulabwani yes, I agree, you want to use the maximum for any bit, which is 6. – tcrosley Feb 24 '15 at 19:08