In this diagram
what would be the beginning state for Q? Since the first NOR for S and R rely on previous results, there must be something for the first iteration?
NOTE: I'm in a first year digital logic class, so the question is for theoretical use (table making, various homework problems it applies to, etc.), not actual implementation. Just for things like "if R is __ and S is __ what is Q?" Simple things like that.
If you just powered that on, the initial state would be the outcome of a race condition, depending on which gate output can become high first. In actuality, one gate or the other would tend to have a faster rise time, so it probably would tend to come up in one state or the other, but there'd be no guarantee.
An RS latch has a stable Q high state and a stable !Q high state, but it also has an essentially infinite number of metastable states. When the latch is in a metastable state, the outputs may arbitrarily switch high and low for an arbitrary length of time, though in practice most metastable states fairly quickly resolve into a stable state.
Suppose that each gate had an output propagation time of precisely one nanosecond, both inputs simultaneously switched from high to low. While the inputs were high, both outputs would be low. Then one nanosecond after they switched, both outputs would be high. A nanosecond later, both outputs would be low, then both high, etc. In practice, the gates aren't going to behave in such perfectly-balanced fashion, of course, but simply imbalancing things won't entirely prevent metastability. No matter how one might try to tweak the circuit, were it not for quantum limitations, it would be theoretically possible to construct a stimulus with one input leading the other by just the right amount to throw the thing into a metastable state for an arbitrary length of time. In practice, one can construct circuits so that extended metastability would require such a precise stimulus that the probability of such a stimulus actually occurring would be infinitesimal. Nonetheless, it's important to be aware of metastability, since it can cause weird and unexpected behaviors.
Just about any latch can be thrown into a metastable state if VDD rises and falls in just the right pattern. Such metastable states will usually resolve pretty quickly, but it's important to note that it's possible for the output of a metastable latch to seem to switch one way and then some time later switch to the opposite state.
The same question was asked and answered there:
How does a latch determine its initial state?
I have added an answer that explains how a desired initial state can be achieved when a flipflop is built by yourself:
https://electronics.stackexchange.com/a/446285/224980
I know that we should not post "link-only" answers, but as this link points to StackExchange again and as my answer is quite long, I think it would be inadequate to copy it here.
I think you just want the truth table.
This is the truth table:
R | S | Q ---+---+------- 0 | 0 | No change 0 | 1 | High(1) 1 | 0 | Low (0) 1 | 1 | Unpredictable
For the last case, Q and Q' are same which is not possible.
