How does a wired AND/OR bus work?

Question

I am studying for an exam, looking at data buses using wired AND and wired OR configurations.

Using tri-state logic, a device is able to gain control of the bus and transmit anything down it.

I don't understand wired AND or wired OR. The way I understand wired AND at the moment, no device has control of the bus and the output stays at a constant voltage (say 5 V) if no devices are attempting to use the bus.

When a device attempts to use the bus the line will be pulled to 0 V. Now if any device attempts to use the bus at the same time, it will never be clear which device is transmitting.

Wired AND is supposed to be active-high, but when a device uses the bus the line goes low. I would have thought this was active-low.

Answer 1

"However when a device attempts to use the bus the line will be pulled to 0V."
That's it exactly: the bus is high only if all devices set it high. Just like in an AND gate the output is high only if all inputs are high.

Tri-state logic is not the way to control the bus; if one device sets it high, and another sets it low, you have a short circuit. Usually there's a passive pullup, which keeps the bus at its high level. Each device controls an open drain FET to pull it low.
Like you said, in this setup there's no way to determine how many devices are pulling it low simultaneously.

This is indeed active high logic: for the AND function the bus is active (high) if all inputs are active (high). If a device pulls the bus low it's just putting a low level on it.

Answer 2

In a common usage case for a wired-AND/wired-OR bus, there exists some means other than the bus by which devices can indicate whether they want attention. If there are five devices which may require attention but a processor has a single interrupt pin, a common solution would be to have the interrupt pin trigger some code that will ask each device in turn if it wants attention (and if so, service it). If the pin is still driven low after all devices have been polled, the polling cycle will repeat (in case a device which didn't want attention when it was first polled decides it wants attention while a later device is being serviced).

In general, a wired-AND/wired-OR bus will be used when there will often be zero devices wanting attention, and when it is useful to optimize for that case. It would be possible to forgo interrupts and simply have code repeatedly query every I/O device to see if it wants attention even when none do, but it is often far more useful to have code doing other things when no devices need attention.

BTW, another approach for using a bus that's electrically configured for wired-AND/wired-OR operation is to have devices only drive the line when explicitly addressed and asked to do so. Despite the electrical similarity, though, such configurations are often not referred to as wired-AND/wired-OR buses, since there's no possibility (when things are working as expected) of combining signals from unknown sources.

Answer 3

Consider there is one bus and 3 drivers, that is, data are coming from all 3 drivers. Consider the driver outputs are binary. If one of the drivers drives the value 1 (HIGH) while other one driving 0 (LOW), that might result in a conflict. To resolve it we use wired OR (bus will be high when at least one input is high) or a wired AND (bus will be high if all inputs are high) etc. These types of functions are called "resolution functions."

Answer 4

You are misunderstanding and/or misusing the phrases "active high" and "active low".

"Active high" means that a high logic level will invoke some behaviour, such as resetting a latch. "Active low" means that a low signal will invoke that behaviour.

In the context of wire-AND or diode-OR, or similar techniques, the terms "active high" and "active low" are inappropriate, but I understand that the terms have been misappropriated for use in this context. This may be a contentious issue (pun intended), but I would deliberately avoid using those terms in the context of a data bus such as I²C.

In a wire-AND scenario, you have a number of participants able to control (to a limited degree) the potential of some node. The mechanism is usually an open-collector or drain, and in such a scenario, any one of those collectors/drains may pull the node to ground potential, or not pull the node to ground potential.

This does not mean that the node is "active high" or "active low". It means only that the node is "pulled up" by some resistor, or current source, and that the only way any connected device has of signalling on that node is by pulling it low. Hence, the node is high only when all devices connected to that node are not pulling low, otherwise known as wire-AND.

There's no way for any of those connected devices to know if the bus is "occupied", in use by someone else, except to sense that it's currently low, which can only happen when some other device is pulling it there. Otherwise, bus contention cannot be detected without some seriously complicated hardware. If the potential of the bus is "high", there's no way of knowing if that's because no-one's using it, or if it's because the device using it is currently outputting a logic 1.

When a device attempts to use the bus the line will be pulled to 0 V. Now if any device attempts to use the bus at the same time, it will never be clear which device is transmitting.

This is correct. But it is also true that even if the bus is currently at logic high, you still can't know if another device is using it, or which device.

For such buses, like I²C, the only way to avoid bus contention is to have some protocol in place to coordinate who gets to say something and when.

Answer 5

tl; dr: In the most common usage, ‘wire-or’ means a bus with a common pull-up resistor, and any device on the bus can pull the line down, but not up.

Historically it was used to create wide fan-in negative-logic OR, and earlier, bussed signals prior to the availability of 3-state logic.

Even after 3-state came available, this ‘any signal low brings the common signal low’ design pattern persisted for a very long time for interrupts, bus arbitration, handshaking and others. This is due to the influence of TTL, which favors active-low for power and noise margin reasons.

Now, what is technically ‘wire-or’? If you have a common pull-up, and you define both your inputs and the common signal to be active-low (very common in TTL), you get a negative-logic OR.

Stated another way, any input brought low brings the bus low.

Likewise, if you define inputs and bus to be active-high, that very same configuration is positive-logic AND. All inputs brought high brings the bus high.

For example, I2C is active high. Drivers detect cases where another device is pulling the bus low:

• master detects slave pulling SCL low to stretch the clock
• master trying to emit SDA high detects another master pulling it low, causing it to let the other master have the bus

It’s also possible, but less common, to build wired-logic gates with a common pull-down and multiple pull-high drivers. This would be a positive-logic OR or negative-logic AND.