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I'm taking my first course in electronic circuits and I'm a little lost when it comes to combining NMOS transistors with capacitors. In particular I am having trouble with finding the steady state for Vo(t) in the following diagram.

Can someone point me in the right direction? My thoughts go as far a recognizing that steady state means there will be no current going though the capacitor as it acts like an open circuit.

The intial conditions are Vin = 0 V and Vo(0) = 0 V (cap is initial uncharged) and phi(t) is turned low(0 V) to high (5 V)

Edit : the parameters of the nmos: \$V_{Tn} = 1 V\$ and \$k_n=1 \mathrm{\frac{mA}{V^2}}\$

enter image description here

VanyaS
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2 Answers2

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Umm, this question can be generalized. Here Vin is 0V, but if Vin is other values, you can think as below.

No matter which region the transistor working, the charging current to the capacitor, that is \$i_{D}\$, should tend to 0. Then we can do some analysis on the \$i_{D}\$'s equation on these two regions.

At nonsaturation region

$$ v_{DS} < v_{GS}-v_{TN}\\ i_{D}=K_{n}[2(v_{GS}-V_{TN})v_{DS}-v_{DS}^2] $$

When \$i_{D} = 0\$, this equation has only one solution, that is \$v_{DS} = 0\$.

At saturation region

$$ v_{DS} > v_{GS} - v_{TN}\\ i_{D}=K_{n}(v_{GS}-V_{TN})^2 $$

When \$i_{D}=0\$, there is \$v_{GS}=V_{TN}\$.

That is, in ideal case (omit the leakage), the capacitor is either charged to \$v_{D}\$ or charged to \$v_{G}-V_{TN}\$.

diverger
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In steady state, due to the capacitor, the current will asymptotically tend to 0, and therefore Vo will become equal to Vi. But as \$phi(t)\$ is applied to the gate of the transistor, you know that the source can only go up to the gate voltage minus \$V_T\$.

clabacchio
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