Function call isn't executed in verilog

Question

Why function call to clogb2 is not being executed in the following code. I don't get any compilation errors but still parameter adder_width is not updated with the value from clogb2. In fact, that function doesn't return any value.

See http://www.edaplayground.com/x/Pxc.

module ram_model ();

   parameter ram_depth = 8;
   localparam adder_width = clogb2(ram_depth);
   initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);
      $monitor("%d",adder_width);
   end

   function integer clogb2;
      input depth;
      integer i,result;
      begin
         for (i = 0; 2**(i) < depth; i = i + 1)
            result = i + 1;
         clogb2 = result;
      end
   endfunction 

endmodule

It might help if you added some details about the actual system / OS / Language you are using ? — Cees Meijer, Nov 26 '14 at 07:51
You really couldn't come up with anything more relevant than [tag:function]? — Ignacio Vazquez-Abrams, Nov 26 '14 at 08:20
I don't know verilog, but it looks like you don't need that function clogb2. See http://stackoverflow.com/q/5602167/1544337 — , Nov 26 '14 at 08:28
@IgnacioVazquez-Abrams I was reading up on constant functions and tasks in verilog and that is how I came up with this code. — Abhi, Nov 26 '14 at 09:37
@CamilStaps I was reading up on constant functions and tasks in verilog and that is how I came up with this code — Abhi, Nov 26 '14 at 09:39
Well, yeah, of course you can write your own code to calculate the 'rounded-down 2-base log of an input plus one'. But you can also use the built-in function, which would be easier. However, it's just a side note, as I said, I don't know verilog, so I don't know what's the problem with this code. — , Nov 26 '14 at 09:58

score 3 · Accepted Answer · answered Nov 27 '14 at 07:04

The function is called but it returns 'x' because your depth argument is only one bit wide and the LSB of 8 is zero, so result is never assigned a value.

Change the line

input depth;

to

input integer depth;

and adder_width will be set to 3 as expected.

Function call isn't executed in verilog

1 Answers1