4

How can I be sure that at boot time my module won't get random values to it's control signals and write to an address* before I reset the module?

*(or anything that shouldn't be done before reset)

If the question is considered too general: I'm trying to make some code in System verilog with a Xilinx Zynq platform as a target device in mind.

user2692669
  • 151
  • 4
  • 3
    You use a power-on-reset circuit to assure that the reset signal is asserted as the power supplies ramp up. –  Nov 10 '14 at 14:53
  • @toolic Can you expand more on that with an answer? – user2692669 Nov 11 '14 at 13:16
  • An answer is beyond the scope of Verilog: http://en.wikipedia.org/wiki/Power-on_reset –  Nov 11 '14 at 13:37
  • possible duplicate of [What happens when an FPGA is powered on and left unconfigured?](http://electronics.stackexchange.com/questions/34378/what-happens-when-an-fpga-is-powered-on-and-left-unconfigured) – Simon Richter Nov 11 '14 at 22:12
  • @SimonRichter It's very different: I'm concerned about what will happen to the module itself (it shouldn't be left unprotected at start cause I may get random I/O signals), I won't try to leave the fpga unconfigured or try to figure something that would harm the board itself. – user2692669 Nov 11 '14 at 23:32
  • You need to elaborate on where your I/O signals are coming from. Inside or outside the FPGA? – mng Nov 12 '14 at 00:47
  • @mng Let me elaborate: The concern was raised while trying to design (my very first) FSM for the Amba axi-4 protocol. Then the thought of having random operations before asserting the reset signal was a nightmare. The inputs and outputs will come either directly from a single Master either from an interconnect component (more likely). So I supose all signals will be internal (I'd like to emmbed the module to a larger system). – user2692669 Nov 12 '14 at 01:48
  • Is there any particular reason you wouldn't be able to use the AXI peripheral reset? – mng Nov 12 '14 at 02:04
  • @mng that do you mean? Is that in the specification? (I'm very new to all these) – user2692669 Nov 12 '14 at 02:07
  • @user2692669, at least it should cover the FPGA side of things: the FPGA is passive, and you should have both an active-low and an active-high output that remains active until the FPGA has been loaded and regular operation started, and these can be used to keep the rest of the logic in reset state. – Simon Richter Nov 12 '14 at 12:12
  • If you're making an AXI peripheral you should have an ARESETn input. Build up a Zynq block diagram and you will see. – mng Nov 13 '14 at 01:35

2 Answers2

1

During the boot sequence the I/O-pins are usualy pulled up with high impedance so they can not damage other parts. For the registers and the memory of the FPGA you can define the initialization with the constraints editor.

If you build the PCB yourself it's your job (with the help of the data sheets) to provide the appropriate reset signals (perhaps sequential) to the various parts. Eventually you will need also some pull-up or pull-down resistors or additional logic. You also have the possibility to control the startup of other parts/modules with your FPGA.

Kitana
  • 792
  • 3
  • 10
0

I agree with Kitana's assessment, to clarify, the usual start-up sequence of an FPGA is something like this:

power rails come up -> FPGA is configured -> reset is issued to FPGA -> the reset statements in your code set the IO to known states.

Hope this helps

Gipsy Danger
  • 346
  • 2
  • 5