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I just saw this question and was wondering how this circuit actually works, since I couldn't really figure it out, I though about asking it.

This is the circuit I am talking about: Circuit

Lets label transistors from left to right as: Q1, Q2, Q3, Q4. I dont really know where to start, how to analyze this circuit to figure it out how it works. What I am especially curious about is the purpose of Q1? Or what about the diode?

If someone could give a detailed description of the circuit I would be really thankfull.

Golaž
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    http://electronics.stackexchange.com/questions/135464/can-a-transistors-emitter-and-collector-be-used-interchangeably – Ignacio Vazquez-Abrams Oct 31 '14 at 14:24
  • I understand the operation of Q1 now, but why would you use it in the first place? Why not tie **Input A** to the base of Q2? What is the advantage of doing it this way? – Golaž Oct 31 '14 at 15:01
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    http://electronics.stackexchange.com/questions/136021/what-is-the-use-of-transistor-in-the-input-side-in-ttl-logic-family – Ignacio Vazquez-Abrams Oct 31 '14 at 15:03
  • What did you mean by "you dont have to worry about the amount of current being fed in"? If there wasnt no Q1, wouldnt you just put the appropriate resistor to the Q2 base? – Golaž Oct 31 '14 at 15:12
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    What would the appropriate resistor be? The chip designer has little to no control over what the end user connects to the chip, so a reverse-biased diode presents the easiest solution. – Ignacio Vazquez-Abrams Oct 31 '14 at 15:14
  • Ah I see, there is a wide range of voltages avaliable as an input. Thanks for the help. – Golaž Oct 31 '14 at 15:17
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    @Golaž also, you can get multiple emitter junctions on those transistors, which allows you to use many inputs as "AND" style inputs, it's easier than having lots of diodes instead. Old style inputs to these gates was done by a simple diode, but this way is low input impedance and multiple inputs made easier by a multi-emitter transistor – KyranF Oct 31 '14 at 15:49

1 Answers1

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Q1 gets input current and voltage, and operates in "reverse active mode" to make current flow from VCC through the 6K Ohm resistor, through the Base, out the collector(!) and into the base of Q2.

Q2 then turns on, sourcing current in the usual fashion into the base of the output arrangement created by Q3 and Q4. When input A is high, Q2 turns on Q3, which grounds Q4 making the output high impedance, letting an external resistor pull up to VCC or whatever it's connected to.

The collector-emitter in Q4 is able to pull towards GND (perhaps not quite reaching GND though), and this is an "Open collector" style logic set-up, because the top (collector!) of Q4 is the connection to the outside world. You would probably have an external pull up resistor on the output, and when Input A is low, it will pull the output close to GND.

KyranF
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  • Q3 and Q4 do not form a Darlington pair. – Matt Young Oct 31 '14 at 14:45
  • @MattYoung ah, yes I see that the collectors are not tied together. by mad. changing now – KyranF Oct 31 '14 at 15:03
  • ... and Q1 is never in "reverse active mode". When the emitter is high (or open), current simply flows from base to collector because that junction is a forward-biased diode. When the emitter is low, the current flows out there instead, cutting off Q2. In this circuit Q1 is primarily being used as a "dual diode"; it is in an active mode only as long as it takes to discharge the base node of Q2. – Dave Tweed Oct 31 '14 at 15:05
  • I had made some edits, I see that it's not a darlington pair at all, and Q3 merely pulls down and also turns off (inverts the logic) of Q4's output – KyranF Oct 31 '14 at 15:11
  • So, whats the deal with the voltage divider formed on Q2 emmitter terminal? Why not tie the Q3 base directly to the Q2's emmitter? – Golaž Oct 31 '14 at 15:19
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    @Golaž my guess is for current limiting, and threshold/voltage input hysteresis. VCC also needs to be a certain voltage for this to work, as there is a 1.1/4.5 ratio for the base-emitter voltage for Q3 here. This means to ensure turn-on at 0.7V the VCC rail must be above ~3V. – KyranF Oct 31 '14 at 15:28
  • Last question, what is the purpose of the diode at the input? – Golaž Oct 31 '14 at 15:29
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    It is merely a clamping diode which limits negative input voltages to only 1 diode drop. It doesnt' affect normal behaviour. – KyranF Oct 31 '14 at 15:46
  • newer CMOS based devices usually have this diode, plus another one to VCC, which is pretty much standard for all CMOS devices due to ESD and other nastyness. @Golaž – KyranF Oct 31 '14 at 15:47
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    @Golaž The reason for using a transistor Q1 at the input (TTL) rather than a diode (DTL) which would also provide an appropriate voltage drop is to quickly discharge the base capacitance of Q2 during the high-to-low transition when teh transistor goes into forward active mode briefly. Without the transistor, the buffer would not switch 'off' as quickly. – Spehro Pefhany Oct 31 '14 at 16:49