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We would like to tightly-couple a FPGA with a µC by means of the external static memory memory controller, thereby effectively mapping the FPGA registers into main memory of the µC with maximum bandwidth. Possible candidates (amongst others?!) are the STM32F4xx and LPC43xx series, both with a 8/16/32-bit parallel External Static Memory Controller.

Of course these parallel interfaces require a lot of IOs (mostly address and data lines) and we are grateful for every pin we can spare.

The STM32 FSMC peripheral provides the ability to multiplex between address and data lines, which saves a lot of pins at the cost of only a single cycle. As far as I can tell, this ability is not mentioned in the LPC43xx datasheet/manual.

Am I missing something in the LPC43xx datasheet, or is this feature really only available in the STM32F4xx family?

Arne
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    If you were only doing contiguous-block access, you probably don't need the address lines anyway - you can just pre-agree or pre-load a starting address (perhaps temporarily use the pins as GPIOs) and auto-increment from there. How many address lines do you need anyway? "Registers" are usually limited in number, implying not very many, while you have a huge address space available so you can probably use a single high order line as a chip select and ignore the rest, accepting aliasing. – Chris Stratton Oct 01 '14 at 17:16
  • @Chris I really would like to allow random instead of auto-increment access. But your suggestion is welcome! – Arne Oct 01 '14 at 17:27
  • How many registers? – Chris Stratton Oct 01 '14 at 17:30
  • @ChrisStratton unknown :-) depends on how well my colleagues wrap their heads around VHDL. I guess 8-bit addresses/data are enough which are 16 IOs then. Still acceptable. – Arne Oct 01 '14 at 17:43
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    It's funny you should mention this. I'm doing this very thing with an STM32F405 using a multiplexed bus. This is not yet debugged as the boards are due back from the EMS in about 2 weeks. You may want to look again, I believe that external 32-bit data bus is not available from the FSMC. – Tut Oct 01 '14 at 18:15
  • @Tut good catch, you have to go to the FMC on the STM32F42x (or 43x) devices to get a 32-bit external memory bus. I too am using an STM32F407's FSMC to access a memory space in an FPGA, but I didn't have the I/O shortage so I'm using de-multiplexed addressing (16b data, 16b address). Happy to pass on my FSMC configuration to give you a starting point if you need it. – markt Oct 01 '14 at 23:28
  • @markt have you tested your setup? Does the FSMC perform any buffering? Can one assume that every read/write is actually passed through to the FPGA? – Arne Oct 02 '14 at 07:13
  • @Arne I'm not sure what you mean by buffering in this context, but yes, every read/write passes through to the FPGA, at least once you get the configuration (particularly the timing) correct. – markt Oct 02 '14 at 08:57

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Seems like all the NXP parts are mssing the multiplexing feature of the STM32 FSMC. This is a pitty since their errata sheets are generally much less intimidating than those of ST. However since at least the DMA bugs have been fixed in the STM32F427 and STM32F429, I'll stay with ST.

Arne
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