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There's a google competition going on at the moment called the little box challenge. It's to design a very efficient AC inverter. Basically the inverter is fed a DC voltage of a few hundred volts and the winning design will be chosen by its ability to produce a 2kW (or 2kVA) output in the most electrically efficient manner. There are a few other criteria to be met but that's the basic challenge and the organizers state that an efficiency greater than 95% is a must.

That's a tall order and it got me thinking about it just as an exercise. I've seen plenty of inverter H bridge designs but they all drive PWM to all four MOSFETs meaning there are 4 transistors contributing to switching losses all the time: -

enter image description here

The top diagram is as I normally read about inverter designs but the lower diagram struck me as a means of cutting switching losses by virtually 2.

I've never seen it before so I thought I'd aske here if anyone else had - maybe there's a "problem" that I don't recognize. Anyway, I decided not to enter the competition if anybody wonders why I'm posting this.

EDIT - just to explain how I think it should work - Q1 and Q2 (using PWM) can generate (after filtering) a "smoothed" voltage that can vary between 0V and +V. To produce the first half cycle of a power AC waveform, Q4 turns on (Q3 off) and Q1/Q2 produced the PWM switching waveforms to make a sinewave from 0degrees to 180. For the 2nd half cycle, Q3 turns on (Q4 off) and Q1/Q2 produces an inverted sinewave voltage using the appropriate PWM timings.

Question:

  • Is there a problem that I'm unaware of in this type of design - maybe EMC emissions or "it just won't work stupid!"
gbulmer
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Andy aka
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  • Maybe I am missing something (or you are pulling my peg-leg, because it *was* [International Talk Like A Pirate Day](http://www.talklikeapirate.com/piratehome.html) yesterday, arrr, me buckos?-). Won't the load only have power flowing 1/2 the time at PWM frequency, arrr? I can understand that that reduces switching loses, but won't that halve the available power in an unpleasant way, arrr, ye lubber? (Corrected for lack of fitin' lingo, arrrr!) – gbulmer Sep 20 '14 at 17:32
  • They do get controlled like that, its benefits are easier seen in a 3phase inverter. I did come across that crazy challenge, the only way I saw of meeting that efficiency was with a resonant converter or other ZCS schemes –  Sep 20 '14 at 17:53
  • @JonRB - do you have a link to it maybe? – Andy aka Sep 20 '14 at 18:26
  • I do, sort of. Such a scheme was used in an inverter I worked on years ago, we wrote a paper ( http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=4677131&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F4664822%2F4676877%2F04677131.pdf%3Farnumber%3D4677131 ) If I could provide a direct link I would. NOTE the sinus quality isn't as good as you could get –  Sep 20 '14 at 18:42
  • @JonRB I couldn't really get to the crux of that because I'm not a member and I'm tight with money LOL – Andy aka Sep 20 '14 at 19:42
  • @gbulmer - take yer eye patch off me heartie – Andy aka Sep 20 '14 at 19:43
  • let me see if I can find my copy - it would have been cleaner if a publically accessible link was used. –  Sep 20 '14 at 20:07
  • I have a textbook with a section on the subject if you're interested in that for an answer, but I don't exactly have a survey of "how it's done in industry" – W5VO Sep 20 '14 at 20:54
  • @W5VO I guess I'm looking to see if the method proposed in my question is somewaht original and useful. I'm not bothered about patents - not in it for the money! If I were I wouldn't be posting. – Andy aka Sep 20 '14 at 22:00
  • Okay, I read without my eye patch, looking at your explanation, thank you. I see the idea. There are many fewer switch transitions on Q3/Q4, so fewer losses. This article [Estimating MOSFET switching losses ...](http://www.eetimes.com/document.asp?doc_id=1225701), though not the application you are describing, does an analysis of many/all of the components of MOSFET losses which is quite interesting (I am no expert in power). I assume you know all that, but it might be a handy check list. – gbulmer Sep 21 '14 at 00:25
  • I've never seen either convention that you mentioned. What I've seen is that either the high side pair or the low side pair is used to determine polarity and the corresponding other one is PWM'ed. Only 1x switching loss that way. That's for brushed DC motors, but I don't see why an inverter can't do it too. It may need to be somewhat smarter than a motor driver in how it monitors and controls the circuit, but it should be possible to get a decent sinusoid after some passive LC filtering. – AaronD Sep 21 '14 at 05:43
  • @andy aka with it being an IEEE paper to a public conference, I got a colleague to d/l it. https://docs.google.com/file/d/0BxW4BDaqkIc2RDVBcnItcXJoQWZ0LVN4S2JQcW9uUHVKZkJZ/edit?usp=docslist_api you will note we went for hysteresis control but that was for other reasons. You will see the space vector explanation of the reduced switching scheme –  Sep 21 '14 at 08:40
  • @AaronD - that sounds a cool way – Andy aka Sep 21 '14 at 09:26
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    My comment doesn't read right. I meant to say, the article [Estimating MOSFET switching losses ...](http://www.eetimes.com/document.asp?doc_id=1225701), might be a handy reference about switching loses *for folks reading your question*. There is a more to them than I had understood. Of course, you might have a better reference, and it might disappear too soon. – gbulmer Sep 21 '14 at 11:34
  • DC/AC Pure Sine Wave Inverter https://www.wpi.edu/Pubs/E-project/Available/E-project-042507-092653/unrestricted/MQP_D_1_2.pdf – LCS Nov 10 '15 at 21:43

1 Answers1

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Can it be done? Yes

Has it been done? Yes

Will it do as expected? half the switching losses? Yes & if care was taken over the right-leg device selection trading speed for conduction losses then you could further improve the powerCore losses.

Quick model with some REALLY badly optimised output filter & not really tuned, just to prove a point & 100kHz switching freq (10kHz appeared to provide reasonable output but an FFT would be required & varying loads: L,C, rect etc... )

Such a scheme does struggle at zero-crossing so the effect on THd would have to be evaluated and determined if it is an accepted limitation.

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