Sorry, but I couldn't find a better title. Consider the following: I have an address/data bus interface. Intended frequency of the D/A bus would be around 10-50MHz.
According to the datasheet of the device in question (OMAP-L138) the maximum clock frequency appears to be around 100MHz (tCLK(min) is specified as 10ns). I would guess that the rise time of the signals would be around 200ps. But this is really just a guess since I wasn't able to get the information from said manual.
Now I was wondering if there was a rule of thumb of how much (length) the traces may differ, e.g. how much A1 may be offset from A2.