What is the cheapest way to synthesize ASICs in small quantities? (5-10 chips). I'm asking for a specific company, not method.
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http://www.mosis.com/ – placeholder Jul 18 '14 at 15:53
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1@René G good luck! – Funkyguy Jul 18 '14 at 15:56
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@placeholder - from the MOSIS website - "MOSIS offers minimum (e.g. 40 die) and medium (500, 2000 die, etc.) quantities". – WhatRoughBeast Jul 18 '14 at 15:58
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3@WhatRoughBeast What? So 40 die vs 10 requested is somehow wrong, but "providing" a solution that wasn't requested is OK? – placeholder Jul 18 '14 at 16:09
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See also ASIC Shuttle Service Disadvantages? and How much does it cost to have a custom ASIC made?
An example shuttle service is eASIC: http://www.bloomberg.com/apps/news?pid=conewsstory&tkr=ZZISK:US&sid=az55yenSBHYA ; the example $45k cost is about what I'd expect.
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Assuming you want digital, and are willing to use 1.8 to 3.3 volt supplies, Altera and Xilinx.
You asked for specific companies, not method, but I'll give you both. At the quantities you're talking about, FPGAs are hands down the way to go, given the above assumptions. Hence the choice of companies.
WhatRoughBeast
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There are many kinds of applications for which FPGAs are not suitable. I'm not sure what the static current draw would be for e.g. a MOSIS ASIC containing a few hundred gates, but I would not be surprised if there were cases where such an ASIC could outperform an FPGA by orders of magnitude. As an example, suppose one wants a device which interfaces 32 ground-connected switches to a shift register plus an interrupt output. When a switch is open, it should be pulled weakly high. When closed, it should be pulled weakly high for 10us once per second. Interrupts from switch closure... – supercat Jul 18 '14 at 17:41
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...should be immediate; those from switch opening should occur at the next polling interval. Nothing overly complicated about such logic, but an implementation with 74xx chips would be rather bulky. An FPGA or CPLD might be able to do it if one used two wires per pin with a resistor between them (the chips I've seen don't allow dynamic control of weak pull-up behavior) but current consumption would probably be higher than ideal. A microcontroller could do it, but it would probably need "advance notice" whenever another controller wanted to read out the port states. – supercat Jul 18 '14 at 17:45
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If one were producing a device that needed such chips in high volume, the performance achievable using an ASIC would probably be far better than the performance using anything else, and the design effort for an ASIC would probably be pretty modest, even if one laid out the artwork by hand. – supercat Jul 18 '14 at 17:47
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@supercat: For specialized applications like that, there are FPGAs designed to address them. For example, Actel (now Microsemi) IGLOO parts are well-suited to power-limited applications. – Dave Tweed Jul 18 '14 at 17:47