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I found the following diagram in data sheet for M74HC595 8 bit shift register M74HC595 Logic Diagram

I have three questions.

  1. Do I understand correctly that all blocks inside red ellipses are NOT gates?
  2. What is the difference between (circle-triangle) and (triangle-circle) symbols?
  3. Why did they put two NOT gates sequentially? These two gates will just pass through unchanged input signal according to NOT truth table. Will the circuit without these two NOTs operate the same way?
Fedor Kotov
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  • And for the final bit, "To maintain timing constraints re slew.". – Ignacio Vazquez-Abrams Jul 08 '14 at 20:31
  • @Ignacio Vazquez-Abrams You are right. This is a duplicate. English is not my native language and I'm a newbie in electronics so I just didn't find the right term (cascaded) to search for before asking the question. – Fedor Kotov Jul 08 '14 at 20:37
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    If one is good, two must be better. – Olin Lathrop Jul 08 '14 at 20:42
  • The question isn't quite a duplicate, IMHO, since it the questions about the difference between triangle-circle and circle-triangle are not answered on the other page. – supercat Jul 08 '14 at 21:13

2 Answers2

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Answers:

  1. Yes

  2. They want to emphasize that the input signal is active high or active low

  3. There is probably that circuit inside (or certainly something very close to two CMOS inverters), to buffer the input, so the input does not have to drive all the flip-flops directly and has no more capacitance than any other input. Also it's frequently required to generate clock and /clock signals inside CMOS logic. Also, as Ignaciao mentions- to sharpen up the edges on the clock signals (not so important on the other inputs).

Spehro Pefhany
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  • Would there be any likely difference in the realization of the two styles of gates (e.g. switching threshold, etc.)? – supercat Jul 08 '14 at 21:14
  • I don't think so, other than the obvious input protection network connected to the input bonding pad, but I'm not an IC designer. – Spehro Pefhany Jul 08 '14 at 21:53
  • `.." clock and /clock.."` - This is what I thought these buffers were normally there for, but this case does not show any utilization of /clock and the double-buffer is present at all inputs. As for his second question, whether the bubble is placed in the front of the back of the symbol has no consequence for the inverter, right? I have seen the bubbles before and after other logic gate symbols - [example](http://www.rfcafe.com/references/electrical/NEETS-Modules/images2/13211img6C.gif) - and of course that makes it mean something completely different. – sherrellbc Jul 09 '14 at 00:42
  • @sherrellbc The clock and /clock are present in most detailed low-level schematics of FFs (eg. CD4027), to drive the halves of transmission gates. http://www.ti.com/lit/ds/symlink/cd4027b.pdf As FiddlyOhm says, the schematics are simplified and high-level and don't necessarily show the details accurately or completely. – Spehro Pefhany Jul 09 '14 at 01:24
  • @SpehroPefhany: I've had a VLSI course, but never designed anything that went to production; by varying the relative sizes of N and P transistors, one could cause a buffer to propagate rising edges slower than falling ones or vice versa. A matched pair of inverters gates would tend to pass through pulses about as long as those going in; an inverter whose output is slow falling, followed by one whose output is slow rising, would extend low-going pulses, while a pair the other way would extend high-going pulses. It's thus plausible that the choice of inverters is meaningful... – supercat Jul 09 '14 at 15:12
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    ...but it's not clear what exact behavior the chip designers would be trying to achieve. – supercat Jul 09 '14 at 15:13
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I would add to Sphero's very good answer that you should not take these IC internal diagrams literally. They are intended to show essential internal functionality, but not necessarily detailed internal structure.

For example, do the D-Flops on the silicon actually have a low-going RESET input as indicated by the diagram? Maybe, maybe not.

Does a low-going pulse on the IC's SCLR- pin clear the IC's Q output pins to Logic 0 (assuming the outputs are enabled by G- pin being held low)? Yes. Does that mean that the internal flops actually utilize their Q output driving a non-inverting output buffer as shown? Or, do the internal flops actually use their Q- outputs and an INVERTING buffer? Either topology is possible and you will never know which is the case as an outside observer.

There are a lot of shortcuts and silicon magic performed in all ICs which is not always easily portrayable in a conventional schematic diagram. Remember, the IC is not made up of individual gates, but transistors. If the manufacturer gave the schematic of the actual transistor circuitry etched into the chip, users would know the exact nature of the internal circuitry, but be deprived of a concise diagram of essential functionality of the chip. That's what these diagrams are meant to portray - essential functionality.

FiddyOhm
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  • By "low-going" do you mean "active-low"? And also, what non-inverting buffer is being driven by the Q outputs? I thought those 3-terminal triangular symbols were tri-state buffers that were either in HI-Z or pass their inputs depending on the state of G. Perhaps some of those tri-state buffers invert their outputs? – sherrellbc Jul 09 '14 at 00:36
  • @sherrellbc: *As shown* the Q outputs and positive-logic enable-low buffers are used. FiddyOhm's point is that you don't know whether that's actually the case or if Q' and inverters are actually being used instead; this is an implementation detail and doesn't belong in the diagram (but it's probably using a transmission gate instead of a tri-state buffer, seeing as how it's simpler that way). – Ignacio Vazquez-Abrams Jul 09 '14 at 05:34