5

A while ago I had a project that involved Analog Devices ADuC812 microconverter.

Amongst assorted on-board hardware, the device had two very helpful DAC converters, that could source 0-5V on their respective pins and even maintain a respectable amperage.

There was one problem though. While the manual said all you had to do was writing a specific value into a specific register, and voltage corresponding to that value would appear on output, the reality wasn't exactly that simple.

One write could move the voltage value by about 3.5V. If you wanted to switch from 0 to 5V you had to perform

 MOV DAC0H,#00fh
 MOV DAC0L,#0ffh

twice. (reversing the order wouldn't help.)

First write would increase the voltage to some 3-and-something volts, and only the second would get it to the right value. If I started from 2V, it would achieve the target 5V in a single write. It's not a big problem, 4 cycles instead of 2 for rapid jumps, no impact for smooth "slides" at all, but it's a weird quirk.

I'd like to ask anyone who worked with that chip - was that just my chip's problem or is this common to all ADuC812? Does it appear in other ADuC family chips? 814 etc?

As a bonus, could someone with electronic knowledge explain how that happens? What internal mechanisms can lead to such behavior?

Jon 'links in bio' Ericson
  • 101
  • 3
SF.
  • 1,108
  • 2
  • 15
  • 27
  • Are you sure you're writing both bytes at once? Can you show the assembly piece? – Dzarda May 21 '14 at 18:43
  • @Dzarda: Now as I recall, there were two halves of the register written separately, but still moving DAC0H from 0 to f should bring the voltage to some 4.68V, and the voltage didn't approach 4. – SF. May 21 '14 at 19:10
  • How do you have DACCON configured? –  May 21 '14 at 19:39
  • @Zack: PD0=1 PD1=1 SYNC=0 CLR0=1 CLR1=1 RNG0=0 RNG1=0 (and 5V attached to VRef) MODE=0. Others changed over the course of testing, but I never bothered with SYNC=1 – SF. May 21 '14 at 20:27
  • VREF is 5V, correct? What is AVDD? –  May 21 '14 at 21:31
  • VRef, AVdd and DVdd were all 5V from the same power unit; the board was their standard evaluation board, not modified in any way (except for attaching a lots of custom circuitry to its IO headers; it included connecting AVdd to VRef.) – SF. May 21 '14 at 21:48
  • @SF: looking at the data sheet, VRef has to be equal or lower than AVdd or weird stuff can happen, but that isn't the case here so scratch that idea. I'd try setting SYNC=1 like Scott suggests –  May 22 '14 at 13:26

1 Answers1

4

The datasheet suggests that DACCON SFR bit 2 (SYNC) needs to be set to 1 for the update to occur as soon as DACXL is written. In your comments you seem to have it set to 0. 1 should be the default value. The table on page 21 indicates that you can use the sync bit to simultaneously change multiple DACs by loading all the registers when SYNC = 0, then set SYNC to 1.

Scott Seidman
  • 29,274
  • 4
  • 44
  • 109
  • ...so, when SYNC is 0, and I load the registers, what is supposed to happen? (what actually happens is the voltage going somewhere *towards* the one given.) – SF. May 21 '14 at 21:14
  • As far as I can tell, nothing should happen until SYNC is set to 1 -- meaning I can't quite explain why writing the value twice causes an update without reading a good deal more about the device. I edited your question with a data sheet link to http://www.analog.com/static/imported-files/data_sheets/ADUC812.pdf, but it's awaiting approval. You'll be interested in page 21. – Scott Seidman May 21 '14 at 21:26
  • 1
    From that it seems like the DACs have three different 'disable' switches: Power, force 0V, SYNC. – SF. May 22 '14 at 08:13