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I am using a pic16f877a for a project and I noticed that there are two VDD and VSS pins. I wanted to know weather all 4 pins had to be connected to power or just one VDD and one VSS pin. A circuit I was working on seemed to work fine with just one connected but I wasn't sure if it was a good idea.

Markovian8261
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    Bottom line, you definitely **should** connect them together (though it may work with them not connected, as you found). There's nothing in the datasheet or midrange reference manual (so far as I can see) that tells you, so I can see why you'd wonder. – Spehro Pefhany May 29 '14 at 21:42

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They have the same name so they share the same function, However, IC's with small packages can have multiple power supply pins with the same function which are not connected together. This is done, for example, to prevent EMC problems. Ground pins are always connected together but may also influence behaviour (stability, error, noise) of certain analog or fast internal components (ADC's, clocks).

Barry
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Your question is answered easily if you think about why there are two couples of power pins. As Barry says sometimes these are just not the same power lines, usually you have to provide a separate \$V_{DD}\$ and sometimes a separate ground for analog functions of the IC. But that does not seem the case.
Sometimes you have multiple power pins just to keep routing simple, you connect what is easier to be connected. Maybe if you want to draw the maximum current from each digital output one pin might not be enough, inside the package there are very thin golden wires that connect the pins to the die, their maximum current might be low.

What I think is that in a big die keeping ground and \$V_{DD}\$ at the same potential, everywhere, is difficult. There are huge spikes of current flowing everywhere, back and forth, and having two low impedance connections to the power supply might be the only solution for the chip designers.

To be extra sure connect all the pins to their respective power tracks, and provide the usual 100nF decoupling capacitor per each couple, as close at the chip as possible.

Vladimir Cravero
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