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I know the following for two positive edge triggered flip flops in cascade.

Max(combinational logic delay) < Tclk_period + Tskew - Tsetup and
Min(combinational logic delay) > Tskew - Thold

But when I consider positive edge ff followed by negative edge ff how will the equation be modified. Will it be:

Max(combinational logic delay) < Tclk_period + (Tclk_period / 2) + Tskew - Tsetup and
Min(combinational logic delay) > Tskew - Thold

or:

Max(combinational logic delay) < (Tclk_period / 2) + Tskew - Tsetup and
Min(combinational logic delay) > Tskew - Thold
JYelton
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Curious
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2 Answers2

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The considerations are exactly the same as for a positive-edge flip-flop. The complicating factor is that, instead of simply the combinational logic delay, you have to add the range of possible propagation delays from the first flip-flop.

WhatRoughBeast
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  • This [link](http://vlsiuniverse.blogspot.com/2013/07/setup-and-hold-checks-static-timing.html) says i have to add clk period for hod time too in this case. They call it half cycle operation. Is this right? – Curious May 15 '14 at 19:30
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Considering a positive-edge triggered FF followed by a negative-edge triggered FF and 1st FF is triggered at t=0 sec. The triggering edge for 2nd FF will arrive only after \$T_{clk} + T_{skew}\$. But the output of 1st FF takes some time (\$T_{clk\rightarrow Q}\$) to settle to a stable value. Stable value should reach at input to the 2nd FF atleast \$T_{setup}\$ seconds before the triggering edge arrives. ie,

$$\frac{T_{clk}}{2} + T_{skew} > T_{clk\rightarrow Q} + T_{logic,max} + T_{setup} $$ or, $$ T_{logic,max} < \frac{T_{clk}}{2} - T_{clk\rightarrow Q} - T_{setup} + T_{skew}$$

The triggering edge to 2nd FF arrives at \$t = T_{clk} + T_{skew}\$. The next triggering edge for 1st FF will happen at \$t =T_{clk}\$ sec, ie., \$T_{clk}/2-T_{skew}\$ sec after triggering 2nd FF. Hence 2nd FF can have a hold time of \$T_{clk}/2-T_{skew}+ min\ delay\ between\ the\ FF's\$. ie., $$T_{hold} < \frac{T_{clk}}{2} - T_{skew} + T_{clk\rightarrow Q,cd} + T_{logic,min}$$ or, $$ T_{logic,min} > \frac{T_{clk}}{2} + T_{clk\rightarrow Q,cd} + T_{hold} + T_{skew}$$

Where, \$T_{clk\rightarrow Q,cd}\$ is the clock to Q contamination delay defined as time taken to produce the first change in output of the FF after applying clock and \$T_{clk\rightarrow Q}\$ is the time taken to make stable change in the FF output after clock is applied.

nidhin
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    Thanks for the answer but i found this [link](http://vlsiuniverse.blogspot.com/2013/07/setup-and-hold-checks-static-timing.html) where it said that such conditions are called half cycle operation and for hold conditions equation will be Tck->q + Tprop + Tsetup < (Tperiod/2) + Tskew (for setup check) and Tck->q + Tprop + (Tperiod/2) > Thold + Tskew (for hold check) can anyone confirm this?? – Curious May 15 '14 at 19:26
  • @user3605217 Thanks for correcting. What you saw in the link is correct. I ve made corrections in my answer. I will try to elaborate the answer. – nidhin May 15 '14 at 20:09