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I'm totally a beginner and my question may seem a little bit stupid, but I would be grateful if you provide any help.

I want to transmit data between my laptop and a Stratix IV GX Development board using RJ45 cable but I don't really know what procedure I should follow. There are tons of reference designs/examples in Altera website (10Gb MAC, Triple-speed ethernet, lots of "application notes", etc.) and I'm completely confused.

I just want to transmit a single bit to the board, invert it and send it back to my laptop, so I don't really need any sophisticated hardware implemented in the board.

I'm familiar with Verilog and design flow using Quartus II software, but not really into communication protocols. It would much help if you provide me some procedure to follow to accomplish this task.

Thanks in advance, Behdad

P.S. I'm using Quartus II 13.1 64-bit on a linux machine.

Roh
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Behdad
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    Small detail you may want to change; there isn't really such a thing as an RJ45 cable. What you have is probably best described as a category 5 or 5e patch cable, or just cat5 for short. RJ45 is the name of the plug end on the cable. It sounds stupid but sometimes an RJ45 plug gets wired different ways or with different qualities of cable. It's really minor, but if you really get into this stuff, it can matter. –  May 01 '14 at 12:41
  • This is a pretty serious FPGA project for a person who has limited knowledge of FPGA, why not start by using a simple USB-to-RS232 interface and communicate via the serial port. – FarhadA May 02 '14 at 15:23
  • Actually yes, this is for a Master's course. The communication between the board and the PC should be fast, the FPGA should act as a coprocessor, so the communication shouldn't be the bottleneck of the whole system. I know there are some "reference designs" on Altera website that demonstrate how to use specific IP cores, but I don't really know which one to get. – Behdad May 02 '14 at 17:08
  • Well, if you just want to sen a single bit of data back and forth, it is much faster to just use a fast RS232 communication that going through the troubles of getting the ethernet up and running. the USB serial interface can go up to 2 megabits/s so I would really recommend using that than making a sophisticated FPGA implementation. – FarhadA May 03 '14 at 08:02
  • As far as I know, Altera provides reference designs for getting IP cores running, so it won't be necessary for me to code anything from scratch. All I need is someone to help me choose a reference design and help me through it. Anyway, thanks for your suggestion, will keep that in mind. – Behdad May 03 '14 at 08:18
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    IF you think it is that simple, I wish you good luck :) – FarhadA May 04 '14 at 12:19

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To discuss with the Ethernet port of your laptop and the development board, you need to use some components mounted on the board.

What you want to do is an ethernet communication. If you are aware of OSI layers, you need to understand the layer 1 and layer 2 for a basic communication between two equipments.

At layer 1 (electrical layer), we will use a PHY which will receive data from the layer 2 (MAC) and convert it into electrical signal on two pairs (10/100Mbps) or four pairs (1Gbps). You will also have a transformer on the path, but on your board it is integrated inside the RJ45 connector.

You have a Marvell 88E1111 PHY on your board which is connected through SGMII to the FPGA. So you need to implement a MAC IP in your FPGA to discuss with the PHY. ( Information here : http://www.altera.com/literature/manual/rm_sivgx_fpga_dev_board.pdf - page 41)

If you take this IP : http://www.altera.com/products/ip/iup/ethernet/m-alt-ethernet-mac.html

You can see on the diagram, that you have the MAC function, which we want. We also have a PCS and PMA functions which are PHY layer functions but are used for the SGMII signal. So you need all these functions.

I'm not a FPGA engineer so I can't provide you a complete how-to, but the best I can say is to read the 802.3 standard about Ethernet, it is free. http://standards.ieee.org/about/get/802/802.3.html Section one : General specs and 10 Mbps
Section two : 100 Mbps
Section three : 1 Gbps

zeqL
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