When trying to drive a high capacitive load why do we gradually increase size of inverters in buffer design. Why not give the output of a circuit to one large inverter?
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About progressive sizing ? – BASIL VARGHESE Apr 02 '14 at 17:37
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1This question makes no sense without some context. – Olin Lathrop Apr 02 '14 at 17:40
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3This comes from VLSI design, where very small transistors are used in internal logic but they must ultimately drive very large transistors in the output buffers. – Joe Hass Apr 02 '14 at 18:21
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@Joe: Then -1 to the OP for not making this clear. "Inverter" could have meant something like a 7400, or something that takes DC and makes AC, and probably a few more. This mess needs to be fixed or closed. Only one more close vote to go. – Olin Lathrop Apr 02 '14 at 19:18
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3@OlinLathrop I suppose you could take it that way, but at that point it seems like you're deliberately going out of your way to be confused. The information he provided *does not make sense* in the contexts you suggested, but it is sufficiently clear (and makes sense) for IC design. – W5VO Apr 02 '14 at 19:48
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2@W5VO: But IC design was never mentioned. Actually when I read the question, my first thought was inverters that make AC from DC, since I just had a recent questions about them on my mind. I'm not a IC designer, so the IC design context never occurred to me. If the OP had mentioned IC design, I would have no problem with this question and would have simply skipped it knowing it was not for me. – Olin Lathrop Apr 02 '14 at 20:01
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1@OlinLathrop To me, it seems a bit backwards that the question should cater to someone who can't (readily) answer the question. This is one of the early concepts in digital IC design, but you wouldn't see it outside of that line of work (the closest thing that comes to mind is multi-stage amplifiers). I'm frustrated because *to me, in this case,* the question is clear. There have been many times when someone is using a specific phrasing or terminology that is only used is a small group of people - and I'm not sure how to discern the difference between (my) personal ignorance and ambiguity. – W5VO Apr 03 '14 at 04:06
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@W5VO: I'm not asking that a question about IC design cater to those that don't know about IC design. We have a bunch of those here, and I usually skip them quickly without incident. The problem here is that it never said it was about IC design. *Inverter* and *buffer* can mean lots of different things even within EE. – Olin Lathrop Apr 03 '14 at 12:18
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Driving a very large inverter from the output of a normal (tiny) logic gate means that a large capacitance will be charged and discharged with tiny transistors. This takes a very long time, causes slow rise/fall transitions on the output pin, and causes considerable power waste in the large inverter.
Depending on the exact process parameters, it usually turns out that the lowest total propagation delay results from having a sequence of inverters. As the signal progresses from the internal logic signal to the output pin the transistors in the inverters get larger, increasing by a factor of 3X to 5X in each successive inverter.
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+1. You might also mention that the method of [logical effort](https://en.wikipedia.org/wiki/logical_effort) can be used to calculate how many intermediate stages will give the lowest total propagation delay; typically a [fan-out of 4 (FO4)](https://en.wikipedia.org/wiki/FO4). – davidcary Apr 03 '14 at 13:36
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Let us assume that we have given the output to one large inverter. Now the signal that has to drive the o/p cap will now see a larger gate capacitance of the large inverter. This results in slow rise or fall times. A unit inverter can drive approximately an inverter that 4 times bigger in size. So we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64. So that each inverter sees a same ratio of o/p to i/p cap. This is the main reason behind going for progressive sizing......
BASIL VARGHESE
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