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I am designing hardware where a specific power up sequence is needed.

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The Vdd_33 should come 10 µs after vdd_18. I have LDOs for these supplies. One option is to control the power distribution with the CPU but this would require either a MOSFET or a second LDO to control the power up. How can I do this in analog domain, without software and GPIOs and MOSFETs?

Kevin Reid
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Ktc
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  • What regulators are you using for the two supplies? Maybe add data sheet links for the google-challenged. – Andy aka Mar 24 '14 at 15:51
  • @Andyaka I will pick something from TI, I haven't designed yet. I am trying to find the right concept first. – Ktc Mar 24 '14 at 16:27
  • @Kte, it's going to be very hard to make an analog power-up sequencer that's cheaper than a couple of (otherwise unused) pins on a micro. – markrages Mar 24 '14 at 17:15
  • 10us or greater or 10us with a tolerance? I take it the supplies are 1.8v and 3.3v. – Andy aka Mar 24 '14 at 17:44
  • Use a "33" regulator with a enable input, and drive that from something that detects the "18" supply being high, plus a little R-C filtering. It would be nice to know what the actual voltages and currents are. – Olin Lathrop Mar 24 '14 at 18:48
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    TI's web-based power supply design tool allows you to specify power up order and delay. – Ignacio Vazquez-Abrams Mar 24 '14 at 21:41
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    The problem with doing it in the analog domain is that you may need to ramp 3.3VDC up second but down first. So an RC delay (or something based on one) doesn't work because the order doesn't reverse on shutdown. You may need something digital to handle proper sequencing. – Matt B. Mar 24 '14 at 23:46
  • @MattB. You are right. I didn't think of that. If you put this as an answer, I will accept it. THanks. – Ktc Mar 25 '14 at 02:31
  • Moreover, adding a single mosfet is way easier than an RC network AND a mosfet. – Vladimir Cravero Mar 26 '14 at 09:43

1 Answers1

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For sequencing power rails to a CPU (where the core and I/O pins run at different voltages), you may need to ramp one of the voltages up first and down last, in order to prevent latch-up. If you try to handle it in the analog domain, it won't work because the rail that ramps up last (due to an RC delay or something based on it) will also ramp down last. Since the required solution has nonlinear behavior, it's probably easier to solve it with something digital, or partially digital with timing set by RC.

There exist special-purpose "power supply sequencer" ICs to handle this problem. Some of them can control as many as 12 power rails. Here's a small one that can control the enable pins of up to 3 voltage regulators.
http://www.ti.com/product/lm3880

More generally, you can find them from the analog IC suppliers such as TI, Maxim and Linear Technology.
http://www.ti.com/lsds/ti/power-management/sequencer-products.page
http://www.maximintegrated.com/products/supervisors/sequencers_trackers/
http://parametric.linear.com/sequencers,_trackers,_and_margining_controllers

Matt B.
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