How to determine an expression that detects underflow?

Question

This is a part of my computer science assignment:

When adding two unsigned binary integers, an overflow can easily be verified by observing the carry out. Specifically, an overflow occurred if and only if S' · Cout = 1.

Does anybody know what this S might represent? is it the sum? if it is how is this expression making sense?

The adder-subtractor circuit also performs the subtraction of the two unsigned integers: A−B.

If the magnitude of B exceeds A, then the subtraction will produce an unusually large result, i.e., an underflow occurred.

1. In terms of the inputs and outputs A3A2A1A0, B3B2B1B0, S3S2S1S0, Cout and S, determine an expression that detects underflow.
2. Determine the simplest Boolean expression that simultaneously detects overflow or underflow.

I have no idea in which direction I should go. I don't even know how to tag this. Can anybody give me a little hint on how to solve them? Like what the answers are supposed to look like?

I think it shouldn't be too hard.

Answer 1

S is the "sign" bit, which is the MSB of the result in 2's complement notation.

Answer 2

Are you sure your quote is accurate? For unsigned numbers an overflow occurs if and only if there is a carry.

IIRC S' . Cout describes the underflow condition for 2's complement addition. There is an underflow when the carry out is different from the carry into the highest bit.

Answer 3

I think \$S\$ is a control bit that determines whether or not a subtraction operation is desired. \$S=1\$ means subtraction. \$S=0\$ means addition. When you add two unsigned numbers together you can ONLY get an overflow and this is always indicated by \$C_{out}=1\$. When you subtract two unsigned numbers you can ONLY get an underflow and this is always indicated by \$C_{out}=0\$ (when subtraction is implemented in the usual way by inverting all the bits of \$B\$ and setting \$C_{in}=1\$. This makes me think that \$S\$ is just \$C_{in}\$ in this case.

If I'm right, then \$S' \cdot C_{out}\$ being the "overflow case" (which can ONLY happen for addition) makes sense. \$S'\$ will be 1 (because addition has \$S=0\$) and if \$C_{out}=1\$ then you have an overflow. That all matches up with what you write, at first. So maybe I'm getting this correct.

Underflow (unsigned and only during subtraction) would then be \$S \cdot C_{out}'\$. So a signal that combines underflow and overflow would be \$S' \cdot C_{out} + S \cdot C_{out}'\$, which is just an xnor between \$S\$ and \$C_{out}\$.