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While researching What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?, I found about various files types. But not all are defined in the Libero SoC or Design Constraints, both v11.2 User's Guides. Specifically what are the files with the suffixes

bfm, cfg, cxf, dat, def, gen, ipd, loc, log, map, pro, rpt, sdb, xml?

This question is the same as List of Xilinx file suffixes (for ISE), but for Actel. I'm not worrying about SmartFusion2 parts, just Igloo2 for now.

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Brian Carlton
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    Maybe the question title should be "What are the various files within Actel (Microsemi)?" I see question titles that mention "List" and initially think it's not going to be a good fit for the SE format. – JYelton Mar 07 '14 at 18:02

2 Answers2

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Partial answer... there are quite a few I don't know, and Libero has decided to segfault when I start it tonight...

  • bfm: Source file - keep under version control. Bus Functional Model script which you write in their ad-hoc language, compile into a .vec file, which is read and executed by a testbench instantiating their VHDL BFM models.
  • cfg: This captures information about the settings that were specified for the system.
  • cxf: SmartDesign core configuration file. This and the matching .sdb allow SmartDesign to recreate the DirectCore components via its "Generate Design" command.
  • dat:
  • def: Discontinued Programming file. Output file from flashpoint.
  • edn: is the Output file.
  • gen: Output netlist file from the generated cores
  • ipd: Programming file
  • loc:
  • log: log file from configured generated cores
  • precision.log: Precision logfile
  • map: lets you know the location of the Logic inside the FPGA
  • _syn.prj: Synplify log file
  • pro: FlashPro settings. Generated by FlashPro.
  • psp: Precision project file
  • rpt: Report. Optionally generated from a menu item in Designer.
  • sdb: Source file - keep under version control. Archive to permit recreation of DirectCore components.
  • srr: Synplify logfile
  • tcl: Used to run synthesis
  • xml: XML files. Some are part of the auto-generated SmartDesign, passing info to the embedded software tools. There may be others.

Additional:

  • prj: Source file - keep under version control. Project file; stores Libero settings for a project
  • adb: Actel Designer database, stores the compiled design for P&R. Output
  • pdb: Actel Designer physical database; essentially the finished bitfile readable by FlashPro
  • vec: Compiled from .bfm
  • pdc: Source file - keep under version control. Constraints such as pinout, I/O standards.
  • sdc: Constraints generated by the tools (e.g. Synplicity). If I modify this I treat it as as source file.

The ones I have listed as Source Files are the ones I keep under version control. I tend to keep all my actual sources OUTSIDE the Libero project structure and "link" them into Libero to minimize interactions between Libero and versioning.

Brian Carlton
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  • Which version control do you use? Do you collaborate with other developers or develop on multiple machines? I've noticed that Libero tends to use absolute paths, which creates problems when collaborating especially when linking files. Do you have a work-around? – kjgregory Aug 26 '16 at 16:19
  • This answer was posted about 7 years ago. I want to know if the toolflow of Actel programming has changed and are there new file types added in 2021? – abunickabhi Oct 06 '21 at 05:01
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Here's what Microsemi said so far. (I'll probably merge the specific files into Brian Drummond's answer and keep the directory information.)

When you create a new project in the Libero SoC it automatically creates new directories and project files. Your project directory contains all of your local project files. If you import files from outside your current project, the files must be copied into your local project folder.

component directory - Stores your SmartDesign components (SDB and CXF files) for your created Libero SoC project.

constraint directory - All your constraint files (SDC, PDC). These are the input files which are used in Synthesis and Place and Route.

designer directory - ADB files (Microsemi Designer project files), -_ba.SDF, _ba.v(hd), STP, TCL (used to run designer), impl.prj_des (local project file relative to revision), designer.log (logfile) *adb is the output

hdl directory - all hdl sources. *.vhd if VHDL, *.v and *.h if Verilog. All these are the input files.

phy_synthesis directory - _palace.edn, palace_top.rpt (palace logfile) and other files generated by PALACE simulation directory - meminit.dat, modelsim.ini files

smartgen directory - GEN files and LOG files from configured generated cores

synthesis directory - *.edn, *_syn.prj (Synplify log file), *.psp (Precision project file), *.srr (Synplify logfile), precision.log (Precision logfile), *.tcl (used to run synthesis) *.edn is the Output file.

Also

*.cfg  This captures information about the settings that were specified for the system

*.bfm  BFM is a stimulus file. These files are provide to Simulation tool.

*.def  Discontinued Programming file. Output file from flashpoint.

*.gen  Output netlist file from the generated cores

*.ipd  Programming file

*.loc  lets you know the location of the Logic inside the FPGA.

From http://soc.microsemi.com/kb/article.aspx?id=SL5622 some programing files are

*.spi Auto Programming, also Cortex-M3 ISP, and In Application Programming (IAP)

*.stp, .ipd,.dat JTAG programming. Also SPI Slave Programming

Brian Carlton
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