I got the impression from answers like this one that the the SS line for SPI is active low. Also from the wikipedia page.
However, I have a DS1305 real time clock. Pages 11, 12 indicate that the CE (chip enable) is active-high. Which I only noticed after I implemented it the other way, wondered what was wrong, and then re-read the datasheet.
There is no question that this device requires CE to be active-high. My question is, is that the normal polarity? Does SPI actually specify which way?
There really is no standard, and this is one of the reasons SPI is such a flexible protocol. Most devices I have seen have active low CS lines, assuming from past convention. For some reason Dallas Semiconductor chose to be different.
SPI-- there are four possibilities of clock polarity and phase, all of which have been used at one time or another.
There is no real standard in one place, just a defacto standard. Usually the Motorola 68HC11 datasheets are pointed to for the origins of SPI.
The original Motorola documents don't include a CE pin, just SS, so no I don't think there is any specification for CE logic. It's normally handled by a GPIO pin anyhow, so the polarity is not very important. It might be more important for SEEPROMs that are talking to an Ethernet chip or things of that nature.
SS is slave select, used to decide who supplies the clock and it's typically tied to a logic level rather than switched. /CE selects the chip that is being addressed and can be used to reset the serial interface, so they're two different things.
