In the 8085 microprocessor there is 64 kb of memory available of which some are assigned to ROM while others are assigned to RAM. My question is, why is ROM always mapped to a lower region of memory map in the 8085 microprocessor?
Asked
Active
Viewed 5,605 times
4 Answers
5
When the 8085 starts up, it will start fetching instructions from address zero. It is thus necessary that the memory which is located there contain defined contents. That does not imply, however, that address zero must be mapped permanently to ROM. One could build a system with e.g. 2K of ROM, 64K of RAM, and a floppy drive, and use an I/O bit to control whether memory reads come from ROM or RAM. On startup, have all reads come from ROM (writes go to RAM regardless of the control bit), and have the ROM program copy itself to RAM. Then enable reads from RAM, and load software from the floppy. Since the bottom portion of the address space would be RAM, software loaded from floppy would be able to set up interrupt vectors for its own purposes--something that would not be possible if ROM were still mapped there.
supercat
- 45,939
- 2
- 84
- 143
-
`LDIR` is a Z80 instruction, and doesn't exist on the 8085. – Dave Tweed Feb 20 '14 at 12:24
-
@DaveTweed: Corrected. If the source and destination address can be identical, I wonder whether it would be faster to use `MOV A,M / MOV M,A / INC L / JNZ / DEC H / JP` or better to use a loop of `POP / PUSH / POP` instructions (I don't know about 8085 timings, but on the Z80, the former sequence would be 10 bytes and take about 28 cycles/byte copied, or 13 bytes and 23/byte if unrolled 2x; the latter would take 11 bytes and take about 22 cycles/byte copied if not unrolled, or 14 bytes and 18.5 cycles/byte if unrolled 2x) – supercat Feb 20 '14 at 13:37
-
@DaveTweed: I suppose with a slight hardware tweak one could make things even faster by having RAM enabled for all memory accesses, but making it so that when ROM is enabled, the RAM's R/W line gets asserted, not that speed really matters for such initialization. I'm curious, BTW, how much "creative addressing hardware" machines included. With addressing hardware equivalent to a smallish CPLD (a few 8-bit latches, a 16-bit ALU, and a few muxes) one could make an 8085 into a decent 16-bit object-oriented CPU accessing 256K of RAM. – supercat Feb 20 '14 at 13:42
-
One example of "creative addressing hardware" would be the Hitachi [HD64180](http://en.wikipedia.org/wiki/HD64180) (a Z80 superset). It had a way of dividing the logical 64 kB address space into up to three regions, each of which could be mapped into a 1 MB physical address space. This fit fairly nicely with the advanced features of the later versions of CP/M, making it possible to to a kind of multitasking, along with RAM disk, floppy disk cache, etc. But by this time, the IBM PC and other 16-bit processors were becoming common, so nothing much more than this was done on 8-bit processors. – Dave Tweed Feb 20 '14 at 14:27
-
In case you're wondering, there's a reason I said 1 MB, and the Wikipedia article says 512 kB. The HD64180 was available in two packages, a 68-pin PLCC and a 64-pin(!) DIP. The high-order address bit (A19) was one of the pins they had to drop in the DIP package, limiting it to 512 kB. – Dave Tweed Feb 20 '14 at 14:32
-
@DaveTweed: That seems fairly "ordinary". My idea would have been to have a range of address space that was available for interrupt use, and a couple of ranges of address space that would could be relocated on 4-byte boundaries. The MMU would continuously latch the last byte fetched from even or odd address in RAM in a non-interrupt area, and a `MOV B,B` or `MOV C,C` would set the upper or lower relocatable area's base to the last fetched word, shifted by two; `MOV A,A` would set the relocatable base to its default. Thus, if one wanted to access byte 4 of an object... – supercat Feb 20 '14 at 14:37
-
...the 160th and 161st bytes of the default base, one would say `mov A,A / lda 80A0h / mov B,B / lda 8004h`. Thus making access to objects in a 256K address space faster than access would normally be even in a 64K address space. I've done somewhat similar (though simpler) tricks on an Atari 2600 game cartridge (which gets 13 address wires, 8 data wires, power, ground, and NOTHING ELSE from the CPU), so I could plot a HIRES pixel at coordinate X,Y of a suitably-arranged bitmap via `LDA $7F00,X / ORA $7E00,Y / STA $7E00,Y`. – supercat Feb 20 '14 at 14:43
3
The 8085 requires ROM a the lowest memory address because, after a reset, it tries to fetch an instruction from location 0. If there was RAM at that address, the processor would fetch random data and would not start the program.
Peter Bennett
- 57,014
- 1
- 48
- 127
1
I know this is old, but here, from memory. As I recall, the 8080 and 8085 usually had a hardware circuit that designers used which was made up of a single gate that would remap memory after three clocks signals - just enough to execute a JMP instruction. So the first memory locations at 0:0 came from an EPROM, and the gate would swap the EPROM with RAM on the 4th clock cycle at 0:0. That's from my memory 30 years ago. I would look for startup hardware circuits for 8085 home built computers - I'm guessing it is there.
Bob McHugh
- 11
- 1
0
ROM always mapped in lower region of memory map in 8085 microproccesor because after reset it tries to fetch an instruction from location o. If there was RAM at that time the address,the processor fetch random data and would no stat the program. So ROM not moved other region.
Nick Alexeev
- 37,739
- 17
- 97
- 230
