-1

I am trying to design a transistor amplifier with a load resistance but I have a lot of problems because the load resistance is very low. I can't change the value of it. I have read a lot about it but I don't know how to procede. Can you please me help me with it?

Model: enter image description here

The only parameters are the load resistance of 100 ohms and must have a gain of -100.

JRE
  • 67,678
  • 8
  • 104
  • 179
Aethox
  • 1
  • 1
  • A lot of missin specs! – Tony Stewart EE75 May 18 '21 at 21:08
  • Is it homework? If it is not, you should give much more context. – user2233709 May 18 '21 at 21:15
  • @user2233709, Yes is a part of lab, the parameters about Ic, Vcc is something that I can choose, I am just learning the procedure with a default hfe, I have read that the load resistance have to be the same as the collector resistance but It makes me a lot of problems with equations – Aethox May 18 '21 at 21:36
  • Since you're new to this, I have to ask.... are you aware this amplifier as drawn will only pass power to your load with an AC signal??? If the input is a pure DC, you will get no amplification at all. If you ARE aware, then consider the amount of power passed (i.e. the load impedance) will be dependent on FREQUENCY. – Kyle B May 18 '21 at 21:46
  • @KyleB, I need gain for an AC signal, the frequency will be higher than 100Hz – Aethox May 18 '21 at 21:48
  • ^^ How much higher than 100Hz??? In the grand scheme of things, 100Hz is almost DC..... – Kyle B May 18 '21 at 21:51
  • Are you running simulations??? Try running them again, but delete C1 & C2 (short circuit them)..... I suspect you'll find that educational – Kyle B May 18 '21 at 21:53
  • @KyleB, Haha you have reason, a signal of 50kHz – Aethox May 18 '21 at 21:54
  • @KyleB, yes I am running simulations, I'll do what you say, thanks – Aethox May 18 '21 at 21:55
  • 50khz, leave C1 where it is. That decouples the input. But do try deleteing C2.... – Kyle B May 18 '21 at 21:56

1 Answers1

2

I'll start you off and see if that helps. Feel free to ask for more.

Given your use of divider in your title, I think I can assume that you know this:

$$A_{v_{_\text{LOADED}}}=A_{v_{_\text{UNLOADED}}}\frac{R_{_\text{L}}}{R_{_\text{L}}+R_{_\text{C}}}$$

You know \$A_{v_{_\text{LOADED}}}=-100\$ and \$R_{_\text{L}}=100\:\Omega\$ but you need to solve this for \$A_{v_{_\text{UNLOADED}}}\$ and \$R_{_\text{C}}\$ before moving on with the design. That's the first trade-off you need to make. If you set \$R_{_\text{C}}\ll R_{_\text{L}}\$, then your loaded voltage gain is about the same value. But that's going to be really hard on the BJT. If you set \$R_{_\text{C}}\approx R_{_\text{L}}\$, then your unloaded voltage gain is about twice as much as your loaded voltage gain and that will be harder to get. But at least it's easier on the BJT.

This takes us onto the turf of perhaps looking more closely at the BJT, itself.

Please note that I'm changing the subject without yet answering the above questions about the resistor selection and the unloaded voltage gain. There's a reason for this. It's because electronics design, in many ways, is like being a stage act where you spin up lots of dishes on thin poles and balance them as you walk around. A lot of times, you don't get to have a straight-ahead, simple flow-chart to follow, putting one piece to bed before going on to the next. It's often a balancing act.

In your BJT stage the quiescent collector current is:

$$I_{\text{C}_\text{Q}}=\frac{V_\text{CC}-V_{\text{C}_\text{Q}}}{R_\text{C}}$$

We know also then that the quiescent dynamic emitter resistance is:

$$r_e= \frac{V_T}{I_{\text{E}_\text{Q}}}$$

Where \$I_{\text{E}_\text{Q}}=I_{\text{C}_\text{Q}}\left(1+\frac1{\beta}\right)\$. But below I'm going to ignore this minor difference and just say that \$I_{\text{E}_\text{Q}}=I_{\text{C}_\text{Q}}\$.

With a completely bypassed (capacitor bypass) emitter resistor and no load at all, the case for maximum AC voltage gain at the collector, the AC voltage gain at that quiescent collector voltage is:

$$A_{v_{_\text{UNLOADED}}} = -\frac{R_\text{C}}{r_e}\approx -\frac{R_\text{C}}{\left[\frac{V_T}{I_{\text{C}_\text{Q}}}\right]}=-\frac{R_\text{C}\:I_{\text{C}_\text{Q}}}{V_T}=-\frac{R_\text{C}}{V_T}\cdot\frac{V_\text{CC}-V_{\text{C}_\text{Q}}}{R_\text{C}}=-\frac{V_\text{CC}-V_{\text{C}_\text{Q}}}{V_T}$$

(\$V_T\$ is the thermal voltage and is usually taken to be between \$25\:\text{mV}\$ and \$28\:\text{mV}\$ for design work.)

So, now it appears that your voltage gain is tied to decisions about \$V_\text{CC}\$ and the quiescent design point for the collector voltage, \$V_{\text{C}_\text{Q}}\$.

Maybe.

If you decide to avoid a full capacitor bypass and apply an emitter resistor, where \$R_\text{E}\gg r_e\$, then the gain is degenerated (and better behaving) to:

$$A_{v_{_\text{UNLOADED}}} = -\frac{R_\text{C}}{R_\text{E}+r_e}\approx -\frac{R_\text{C}}{R_\text{E}}$$

This second case doesn't appear to depend upon the collector voltage or the supply voltage. (Though those are still important.)

Either way, there are tradeoffs to be made.

But you have locked down some relationships, anyway. And at least two different ways to go.

Now, there's more. It is the case that \$V_\text{CC}\$ matters also because the voltage swing magnitude across the load also matters. If your output signal could be \$A_v=-100\$ times an input signal of exactly \$0\:\text{V}\$ then the circuit gets really simple. (Too simple.) But if your input signal is one volt, peak to peak, then the output signal is a hundred volts, peak to peak. Obviously, this impacts \$V_\text{CC}\$!

So you will also need to figure out in your head how much of a voltage swing you want to permit in your design. For that, you will need to figure out what will succeed as a good argument for your work product when it is handed it. You may have to defend your choice!

Does any of this help you think more about designing the amplifier stage?

Or do you need more?

jonk
  • 77,059
  • 6
  • 73
  • 185