I'd like to shamelessly use the figure from Peter's excellent answer:
If you look closely, you'll notice that while the rising edges might be in different positions, the falling edges are always one bitlength apart.
Thus, to measure the speed, you'd wait for the first falling edge (start of Start bit), then count the CPU cycles till the rising edge. Since you know that this is the start bit, you now have a "half bitlength", which, especially, should be the threshold between counting a bit as 1 or 0.
So, how to write a receiver for this depends on the microcontroller you're using, and I'm not versed with AVRs. But: you can normally just assign an interrupt to a pin that gets triggered when the pin changes
In the interrupt service routing (ISR) you'd then check whether it was a falling or rising edge:
- falling edge start a counter that automatic increases without you needing to do anything in software.
- rising edge:
- first bit: stop counter, use as threshold value between
0
and 1
- subsequent bits: stop counter, compare to saved threshold value. If
counter > threshold
: you received a 1
; if counter <= threshold
, a 0
. If this is the eigth bit, go back to "waiting for first bit" state.
There's actually microcontrollers that have hardware receivers for this kind of data. It's not that hard to implement, actually, as you saw from my software logic description above – that's a four-states¹ state machine, and thus relatively easy to implement in hardware. Anyway, my guess is that ATMegas don't have a PWM measurement unit (unlike cheaper alternatives like several of the Cortex-M0 ARM MCUs that e.g. ST Micro sells).
I actually think you might be able to convince your UART to receive this stuff – you'd have to configure your UART to three times (or more) the bit rate of the sensor, and then interpret 011
as 1
, and 001
as 0
, and ignore the start bit. But that'll not be a good solution – since it's not specified in the datasheet, as far as I can see, the bitrate will probably vary a lot.
¹ following a discussion by Wossname: The four states could be
- Waiting for falling edge starting the start bit
- Waiting for rising edge in start bit
- Waiting for falling edge starting a data bit
- Waiting for rising edge in data bit