Xilinx Vivado: [Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

Question

I have a vivado project containing a Xilinx IP core. A tcl script was generated for this project and contains links to the IP core source. The .tcl script and IP source files (xml, xci and veo files) have been added to version control.

When I run the TCL script to create the project, it works fine. However, right-clinking on the IP in vivado and selecting "generate output products" in order to generate the synthesis files produces the following error:

[Common 17-53] User Exception: Unable to launch Synthesis run. No Verilog or VHDL sources found in project

Deleting and re-adding the IP files doesn't fix the issue.

How do I use the tcl script to include and regenerate IP sources?

Answer 1

The tcl script also creates a design run for the IP core. This is seen in the following lines in the script:

# Create 'clk_wiz_0_synth_1' run (if not found)
if {[string equal [get_runs -quiet clk_wiz_0_synth_1] ""]} {
  create_run -name clk_wiz_0_synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset clk_wiz_0
} else {
  set_property strategy "Vivado Synthesis Defaults" [get_runs clk_wiz_0_synth_1]
  set_property flow "Vivado Synthesis 2014" [get_runs clk_wiz_0_synth_1]
}
set obj [get_runs clk_wiz_0_synth_1]
set_property "constrset" "clk_wiz_0" $obj

I replaced the above with the following line:

create_ip_run [get_files -of_objects [get_fileset sources_1] $origin_dir/path/to/xci/clk_wiz_0/clk_wiz_0.xci]

Which creates a run containing the IP and fixed the error.